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AssigneeInternational Business Machines Corporation
InventorsGuy L. Guthrie, William J. Starke, Jeffrey A. Stuecheli, Derek E. Williams
Estimating the term…
In an entry of a first cache memory within a first coherency domain of a data processing system including at least first and second coherency domains, a coherency state field is set to a first state that indicates that an associated address tag is valid, an associated storage location does not contain valid data, and a memory block identified by the address tag is likely cached outside the first coherency domain. In response to snooping a castout operation, the first cache memory determines if the castout operation hits in the entry and, if so, updates the coherency state field from the first state to a second state indicating that the associated address tag is invalid.
A method of data processing in a cache coherent data processing system including at least first and second coherency domains, said method comprising:
A cache coherent data processing system, comprising:
A cache memory for a cache coherent data processing system including at least first and second coherency domains each including at least one processing unit, wherein said first coherency domain includes the cache memory and said second coherency domain includes another coherent cache memory, said cache memory comprising:
Dependencies are inferred from the claim text.
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Cache consistency protocols: using a bus scheme, e.g. with bus monitoring or watching means
Multiuser, multiprocessor or multiprocessing cache systems: with a network or matrix configuration
Computing and data processing
Term ended 4 Jul 2026 (estimated)
The present application is related to U.S. patent application Ser. No. 11/055,305 now U.S. Pat. No. 7,389,388, which is assigned to the assignee of the present invention and incorporated herein by reference in its entirety.
1. Technical Field
The present invention relates in general to data processing and, in particular, to data processing in a cache coherent data processing system.
The novel features believed characteristic of the invention are set forth in the appended claims. However, the invention, as well as a preferred mode of use, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIG. 1 is a high level block diagram of an exemplary data processing system in accordance with the present invention;
FIG. 2 is a more detailed block diagram of a processing unit in accordance with the present invention;
With reference now to the figures and, in particular, with reference to FIG. 1, there is illustrated a high level block diagram of an exemplary embodiment of a cache coherent symmetric multiprocessor (SMP) data processing system in accordance with the present invention. As shown, data processing system 100 includes multiple processing nodes 102a, 102b for processing data and instructions. Processing nodes 102a, 102b are coupled to a system interconnect 110 for conveying address, data and control information. System interconnect 110 may be implemented, for example, as a bused interconnect, a switched interconnect or a hybrid interconnect.
In the depicted embodiment, each processing node 102 is realized as a multi-chip module (MCM) containing four processing units 104a-104d, each preferably realized as a respective integrated circuit. The processing units 104a-104d within each processing node 102 are coupled for communication by a local interconnect 114, which; like system interconnect 110, may be implemented with one or more buses and/or switches.
The devices coupled to each local interconnect 114 include not only processing units 104, but also one or more system memories 108a-108d. Data and instructions residing in system memories 108 can generally be accessed and modified by a processor core in any processing unit 104 in any processing node 102 of data processing system 100. In alternative embodiments of the invention, one or more system memories 108 can be coupled to system interconnect 110 rather than a local interconnect 114.