Method, apparatus, and a system for efficient context switch
AssigneeIntel Corporation
InventorsPeter C. Brink, Shrikant M. Shah, Peter R. Munguia
Life of this patent
Estimating the term…
Abstract
A discussion of a local memory with at least a command block section and a cache section that facilitates an efficient interrupt processing. The command-block section is allocated on a per interrupt basis and contains pointers to cache-lines. When an interrupt is recognized an interrupt, the proposal uses the pointers in the command-block to prefetch the corresponding cache-lines from the cache section of the local memory, which it loads into its local cache buffer. Thus, when the CPU recognizes an interrupt, the information for the context-switch is already available in cache.
Claims20
A method for facilitating a context switch comprising:
- allocating a command block section of a memory on a per interrupt basis and the command block section to store pointers to a cache section of the memory;
- and
- utilizing the pointers in the command block section of the memory to prefetch the corresponding cache lines of the cache section of the memory.
An article of manufacture comprising:
- a machine-accessible storage medium having a plurality of machine readable instructions, wherein when the instructions are executed by a system, the instructions provide an interrupt service routine for:
- allocating a command block section of a memory on a per interrupt basis and the command block section to store pointers to a cache section of the memory;
- and
- processing the interrupt by searching for the pointers in the command block section of the memory, and to prefetch the corresponding cache lines of the cache section of the memory based at least in part on the pointers.
An apparatus comprising:
- a hardware logic to assign an index for each interrupt;
- the apparatus to request a prefetch from a predetermined section of a main memory, the predetermined section of the main memory based at least in part on the index for the interrupt;
- and
- a local memory, having a command block section and a cache section, to store the prefetch from the predetermined section of a main memory in the cache section of the local memory, the predetermined section of the main memory based at least in part on the index for the interrupt stored in the command block section of the local memory.
A system comprising:
- a processor, the processor to halt execution upon receiving an interrupt;
- a dynamic random access memory, coupled to the processor, to serve as a system memory;
- a local memory, coupled to the processor, with a command block section and a cache section,
- the local memory to allocate the command block section of the local memory on a per interrupt basis and the command block section to store pointers to the cache section of the memory;
- and
- the system to process the interrupt by searching for the pointers in the command block section of the memory, and to prefetch the corresponding cache lines of the cache section of the memory based at least in part on the pointers.
Dependencies are inferred from the claim text.