Method and system for maximum residency replacement of cache memory

A cache way replacement circuit for operation in association with a digital signal processor, said cache way replacement circuit for replacing one of a plurality of set ways of a cache memory in the event of a cache tag miss and comprising:

• victim way selection circuitry for selecting a victim way as a cache way that is to be replaced according to a position of said cache way on a FIFO cache way listing of cache ways for use in the operation of the digital signal processor;
• FIFO cache way listing populating circuitry for placing at the end of said FIFO cache way listing subsequent cache tag misses to said cache memory reusing a victim way on a next cache tag miss;
• and
• cache way reuse hazard detection circuitry for preventing reuse of a victim way until initial allocation of said victim way completes, avoiding incoherency between the cache tag and said cache memory by stalling a response to a reuse request until such initial allocation of said victim way completes and replaying a reuse request until such initial allocation of said victim way completes.

A digital signal processor including means for replacing one of a plurality of set ways of a cache memory in the event of a cache tag miss, the digital signal processor comprising:

• means for selecting a victim way as a cache way that is to be replaced according to a position of said cache way on a FIFO cache way listing of cache ways for use in the operation of the digital signal processor;
• means for placing at the end of said FIFO cache way listing subsequent cache tag misses to said cache memory
• reusing a victim way on a next cache tag miss;
• and
• means for preventing reuse of a victim way until initial allocation of said victim way completes avoiding incoherency between the cache tag and said cache memory by stalling a response to a reuse request until such initial allocation of said victim way completes and replaying a reuse request until such initial allocation of said victim way completes.

A computer usable storage medium having computer readable program code means embodied therein for processing instructions on a digital signal processor for replacing one of a plurality of set ways of a cache memory in the event of a cache tag miss, said computer readable medium comprising:

• computer readable program code means for selecting a victim way as a cache way that is to be replaced according to a position of said cache way on a FIFO cache way listing of cache ways for use in the operation of the digital signal processor;
• computer readable program code means for placing at the end of said FIFO cache way listing subsequent cache tag misses to said cache memory reusing a victim way on a next cache tag miss;
• and
• computer readable program code means for preventing reuse of a victim way until initial allocation of said victim way avoids incoherency between the cache tag and said cache memory by stalling a response to a reuse request until such initial allocation of said victim way completes and replaying a reuse request until such initial allocation of said victim way completes.