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US 7,584,321 B1Granted
Memory address and datapath multiplexing
AssigneeNVIDIA Corporation
InventorsChris Alan Malachowsky, David G. Reed, Sean Jeffrey Treichler, Brad W. Simeral
Life of this patent
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Abstract
Circuits, methods, and apparatus for multiplexing addresses and data at a memory interface such that multiple data widths are provided without the need to change a motherboard or other printed circuit board design. A specific embodiment of the present invention achieves this using a single integrated circuit design where the datapath width is selected using a bonding option, fuse, data input, or other selection mechanism. The specific embodiment supports both 64 and 128-bit datapaths, though other numbers of datapaths, and other datapath widths are supported by other embodiments.
Claims24
A computing system comprising:
- a central processing unit;
- a first memory bank;
- a second memory bank;
- and
- a circuit having a first interface configured to send and receive data to and from the central processing unit, and a second interface configured to write and read data to and from the first memory bank and the second memory bank,
- wherein the second interface comprises:
- a first memory controller coupled to a first address bus, a first data bus, a second address bus, and a second data bus;
- and
- a second memory controller coupled only to the second address bus and the second data bus, wherein the first and second memory controllers are each coupled with the first interface,
- wherein the second interface is configurable such that the first memory controller provides a first address on the first address bus and the second address bus at the same time, and a first plurality of data bits on the first data bus and the second data bus at the same time, and
- wherein the first address bus and first data bus are coupled to the first memory bank, and the second address bus and second data bus are coupled to the second memory bank.
8 more elements
An integrated circuit comprising:
- a first interface configured to send and receive data to and from a central processing unit, and a second interface configured to write and read data to and from a first memory bank and a second memory bank;
- wherein the second interface comprises:
- a first memory controller coupled to a first address bus, a first data bus, a second address bus, and a second data bus;
- and
- a second memory controller coupled to the second address bus and the second data bus,
- wherein the second interface is configurable such that the first memory controller provides a first address on the first address bus and the second address bus at the same time, and a first plurality of data bits on the first data bus and the second data bus at the same time, and
- wherein while the first memory controller provides a first address on the first address bus and the second address bus at the same time, and a first plurality of data bits on the first data bus and the second data bus at the same time, the second memory controller is disabled.
4 more elements
An integrated circuit comprising:
- a first memory controller having a data input, a data output, and a first address output;
- a second memory controller having a data input, a data output, and an address output;
- a first plurality of pads to couple to a first address bus and a first data bus;
- a second plurality of pads to couple to a second address bus and a second data bus;
- a first plurality of input/output circuits coupled to the first plurality of pads;
- a second plurality of input/output circuits coupled to the second plurality of pads;
- a first multiplexer having a first input coupled to the first plurality of input/output circuits, a second input coupled to the second plurality of input/output circuits, and an output coupled to the first memory controller data input;
- a second multiplexer having a first input coupled to the first memory controller first address output, a second input coupled to the second memory controller address output, and an output coupled to the second plurality of input/output circuits;
- and
- a third multiplexer having a first input coupled to the first memory controller data output, a second input coupled to the second memory controller data output, and an output coupled to the second plurality of input/output circuits,
- wherein when the first input of the second multiplexer is selected, the first memory controller simultaneously provides an address to the first plurality of input/output circuits and the second plurality of input/output circuits, and when the first input of the third multiplexer is selected, the first memory controller simultaneously provides data to the first plurality of input/output circuits and the second plurality of input/output circuits and
- wherein the second memory controller is not coupled to the first address bus and the first data bus.
9 more elements
A memory interface circuit comprising:
- a first memory controller coupled to a first address bus, a first data bus, a second address bus, and a second data bus;
- and
- a second memory controller coupled to the second address bus and the second data bus,
- wherein the memory interface is configurable such that the first memory controller simultaneously provides a first address on the first address bus and the second address bus and the first memory controller simultaneously provides a first plurality of data bits on the first data bus and the second data bus;
- wherein the memory interface is alternately configurable such that the first memory controller provides a first address on the first address bus and a first plurality of data bits on the first data bus, and the second memory controller provides a second address on the second address bus and a second plurality of data bits on the second data bus, and
- wherein while the first memory controller simultaneously provides a first address on the first address bus and the second address bus and the first memory controller simultaneously provides a first plurality of data bits on the first data bus and the second data bus, the second memory controller is disabled.
3 more elements
A method of multiplexing data at a memory interface comprising:
- performing a first memory access by:
- providing a plurality of first addresses on a first address bus for a first memory bank using a first memory controller;
- and
- providing a plurality of first data bits on a first data bus for the first memory bank using the first memory controller;
- and
- selectively determining whether to perform a second memory access by:
- providing a plurality of second addresses on a second address bus for a second memory bank using the first memory controller;
- and
- providing a plurality of second data bits on a second data bus for the second memory bank using the first memory controller, wherein the plurality of first data bits are different from the plurality of second data bits;
- or
- whether to perform a third memory access by:
- providing a plurality of second addresses on the second address bus for a second memory bank using a second memory controller;
- and
- providing a plurality of second data bits on the second data bus for the second memory bank using the second memory controller;
- wherein while providing a plurality of second addresses for a second memory bank using the first memory controller and providing a plurality of second data bits for the second memory bank using the first memory controller, the second memory controller is disabled.
12 more elements
A method of multiplexing data and address signals at a memory interface comprising:
- providing a first address to a first memory bank using a first memory controller address port;
- providing a first plurality of data bits to the first memory bank using a first memory controller data port;
- selectively providing a second address to a second memory bank by multiplexing the first memory controller address port and a second memory controller address port;
- and
- selectively providing a second plurality of data bits to a second memory bank by multiplexing the first memory controller data port and a second memory controller data port,
- wherein the second memory controller data port and address port only provide addresses and data to the second memory bank.
3 more elements
Dependencies are inferred from the claim text.