Sliced crossbar architecture with no inter-slice communication
AssigneePasternak Solutions LLC
InventorsStephen Clark Purcell, Scott Kimura
Life of this patent
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Abstract
A memory crossbar adapted to transmit a memory transaction to a network resource. The memory crossbar includes a plurality of input ports. Each of the plurality of input ports includes a TAGS generator and a queue adapted to receive a first portion of a first memory transaction and a first portion of a second memory transaction. Each of the plurality of inputs ports also includes an arbiter coupled to the queue and adapted to independently select either the first portion of the first memory transaction or the first portion of the second memory transaction based on a priority associated with the first portion of the first memory transaction and the first portion of the second memory transaction and a multiplexer coupled to the arbiter.
Claims30
A method of processing memory transactions between a plurality of processors and a plurality of shared memories, wherein a plurality of interconnected crossbar switches in a multi-stage crossbar network provides a communications path between the plurality of processors and plurality of shared memories, the method comprising:
- receiving a plurality of memory transactions at a crossbar switch, each memory transaction having been divided into a plurality of associated portions, each portion comprising an address corresponding to a target resource, wherein each crossbar switch comprises a plurality of slices for processing the plurality of associated portions of a received memory transaction in parallel;
- assigning a priority to each received portion in each slice, wherein each slice independently assigns the same priority to each associated portion of a given memory transaction;
- and
- forwarding each of the plurality of portions to its corresponding target resource based on the address and the assigned priority, wherein each slice independently forwards each associated portion of a given memory transaction at substantially the same time.
An apparatus comprising:
- a plurality of interconnected crossbar switches in a multi-stage crossbar network, the network configured to provide a communications path between a plurality of processors and a plurality of shared memories, wherein an individual crossbar switch comprises a plurality of crossbar slices, wherein the individual crossbar switch is configured to receive a plurality of memory transactions, wherein each crossbar slice of the individual crossbar switch is configured to receive a corresponding associated portion of a memory transaction, and wherein each crossbar slice of the individual crossbar switch is configured to independently forward its corresponding associated portion of the received memory transaction to a target resource at substantially the same time.
An apparatus comprising:
- a plurality of interconnected switching means in a multi-stage switching network, the network configured to provide a communications path between a plurality of processors and a plurality of shared memories, wherein an individual switching means comprises a plurality of slices, wherein the individual switching means is configured to receive a plurality of memory transactions, wherein each slice of the individual switching means is configured to receive a corresponding associated portion of a memory transaction, and wherein each slice of the individual switching means is configured to independently forward its corresponding associated portion of the received memory transaction to a target resource at substantially the same time.
A computer readable media with instructions to cause a microprocessor to perform a method of processing memory transactions between a plurality of processors and a plurality of shared memories, wherein a plurality of interconnected crossbar switches in a multi-stage crossbar network provides a communications path between the plurality of processors and plurality of shared memories, the method comprising:
- receiving a plurality of memory transactions at a crossbar switch, each memory transaction having been divided into a plurality of associated portions, each portion comprising an address corresponding to a target resource, wherein each crossbar switch comprises a plurality of slices for processing the plurality of associated portions of a received memory transaction in parallel;
- assigning a priority to each received portion in each slice, wherein each slice independently assigns the same priority to each associated portion of a given memory transaction;
- and
- forwarding each of the plurality of portions to its corresponding target resource based on the address and the assigned priority, wherein each slice independently forwards each associated portion of a given memory transaction at substantially the same time.
Dependencies are inferred from the claim text.