Protocol conversion circuit
AssigneeFujitsu Limited
InventorsYuki Sakai, Katsuhiro Yoda
Life of this patent
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Abstract
A protocol conversion circuit performing a protocol conversion between a preceding stage circuit and a succeeding stage circuit includes a data storing unit storing input data from the preceding stage circuit, an output enable signal generating unit generating an output enable signal outputting data stored in the data storing unit to the succeeding stage circuit by using one or more parameters for the protocol conversion which are externally fed and can take a different value each time interval externally specified, and an address specifying unit specifying an address for read of an output data for the data storing unit based on the output enable signal.
Claims12
A protocol conversion circuit performing a protocol conversion between a preceding stage circuit and a reconfigurable circuit provided in a succeeding stage, comprising:
- a data storing unit to store input data from the preceding stage circuit;
- an output enable signal generating unit to generate an output enable signal for outputting data stored in the data storing unit to the reconfigurable circuit on a basis of configuration information of the reconfigurable circuit;
- an address specifying unit to specify an address for read of an output data for the data storing unit based on the output enable signal;
- and
- a start signal generating unit to output a start signal to the output enable signal generating unit at a time point when storing of an initial input data is started for a time interval externally specified in the data storing unit, wherein
- the output enable signal generating unit generates an output enable signal which is delayed, by a number of clocks specified with a parameter, from an input time point of the start signal.
A protocol conversion circuit, which is a circuit performing a protocol conversion between a plurality of preceding stage circuits and a plurality of reconfigurable circuits provided in a succeeding stage corresponding to the respective preceding stage circuits, comprising:
- a plurality of data storing units respectively storing input data from the plurality of preceding stage circuits;
- a start signal generating unit receiving a start signal output from each of the data storing units at a time point when storing of initial data is started for each time interval externally specified in the plurality of data storing units, and outputting a real start signal upon receipt of the start signals from all of the plurality of data storing units;
- and
- an output enable signal generating unit generating an output enable signal on a basis of configuration information of the plurality of reconfigurable circuits and feeding the generated output enable signal to each of the data storing units, wherein
- the output enable signal is a signal for outputting data stored in each of the data storing units to the plurality of reconfigurable circuits, is shared by the plurality of data storing units, and is delayed, by a predetermined number of clocks specified by the configuration information, from an input time point of the real start signal.
A protocol conversion circuit, which is a circuit for performing a protocol conversion between a plurality of preceding stage circuits and a plurality of reconfigurable circuits provided in a succeeding stage corresponding to the respective preceding stage circuits, comprising:
- a plurality of data storing units for respectively storing input data from the plurality of preceding stage circuits;
- a start signal generating unit receiving a start signal output from each of the data storing units at a time point when storing of initial data is started for each time interval externally specified in the plurality of data storing units, and outputting a real start signal upon receipt of the start signals from all of the plurality of data storing units;
- and
- a plurality of output enable signal generating units generating an output enable signal on a basis of configuration information of the plurality of reconfigurable circuits and feeding the generated output enable signal to each of the data storing units, wherein
- the output enable signal is a signal for outputting data stored in each of the data storing units to the plurality of reconfigurable circuits, is an independent output enable signal for each of the plurality of data storing units, and is delayed, by a predetermined number of clocks specified by the configuration information, from an input time point of the real start signal.
Dependencies are inferred from the claim text.