Packet manager interrupt mapper
AssigneeBroadcom Corporation
InventorKoray Oner
Life of this patent
Estimating the term…
Abstract
A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with an interrupt mapper for informing a plurality of processors about system-related functions for a plurality of channels. Using status registers containing interrupt status information for the plurality of channels, interrupt sources are specifically assigned to individual processors in the multiprocessor device so that the assigned processor can efficiently determine the source and priority of an interrupt by reading the register information.
Claims16
In an integrated circuit multiprocessor switching device, an apparatus for mapping a plurality of interrupts and a plurality of virtual channels through a packet manager to route data packets between external devices and a plurality of processors, comprising:
- an interrupt status register for storing the interrupts;
- mask registers associated with the virtual channels for selectively masking contents of the interrupt status register for each of the virtual channels, the virtual channels for routing the data packets;
- a merged interrupt indication register associated with each virtual channel for storing masked interrupt values for the virtual channels that are obtained after masking and merging the contents of the interrupt status register with the mask registers;
- an interrupt mapping register associated with each virtual channel for storing a processor identification for routing masked interrupt value of a respective virtual channel to a selected processor of the plurality of processors;
- a demultiplexing circuit coupled to the merged interrupt indication register and the interrupt mapping register for coupling the masked interrupt value for each virtual channel to a corresponding one of the selected processors to selectively route the masked interrupt values in the packet manager.
An interrupt mapper in a packet manager for mapping interrupts for a plurality of virtual channels to a plurality of processing cores to route data packets between the processing cores and external devices, comprising:
- a plurality of interrupt registers, where each interrupt register identifies an interrupt for one or more of the plurality of virtual channels, the virtual channels for routing the data packets;
- a mask register associated with each of the plurality of interrupt registers for selectively masking contents of the interrupt register to generate a masked interrupt for each virtual channel;
- a channel merge circuit for merging the masked interrupt for each virtual channel into an interrupt indication value for each respective virtual channel;
- a channel register that stores the interrupt indication values for the plurality of the virtual channels;
- a plurality of processor map storage devices, each processor map storage device storing a processor identification value for respective one of the plurality of virtual channels;
- and
- a demultiplexer coupled to the channel register and the plurality of processor map storage devices for mapping each interrupt indication value for a virtual channel to a corresponding one of the selected processing cores identified by the processor identification for that respective virtual channel to selectively route the interrupt indication values in the packet manager.
Dependencies are inferred from the claim text.