System for supporting partial cache line write operations to a memory module to reduce write data traffic on a memory channel

A data processing system, comprising:

• a processor;
• and
• a memory coupled to the processor, wherein the memory comprises one or more memory modules, and wherein each memory module of the one or more memory modules comprises:
• a memory hub device integrated in the memory module;
• and
• a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises:
• burst logic integrated in the memory hub device, wherein the burst logic determines an amount of write data to be transmitted to the set of memory devices and generates a burst length field corresponding to the amount of write data;
• and
• a memory hub controller integrated in the memory hub device, wherein the memory hub controller controls the amount of write data that is transmitted using the burst length field and wherein the memory hub device transmits the amount of write data on a memory channel, wherein the amount of write data is equal to or less than a conventional data burst amount for the set of memory devices, wherein the memory hub controller controls the amount of write data that is transmitted by generating a data mask control signal and wherein the data mask control signal causes a memory device data interface to transmit, as valid write data, only a portion of the data input to the memory device data interface corresponding to the amount of write data determined by the burst logic, wherein the memory hub controller controls the amount of write data that is transmitted by generating the data mask control signal based on the burst length field and transmits the data mask control signal to the memory device data interface within one clock cycle of inputting the data to the memory device data interface.