Fast hardware divider

A divider comprising:

• a divisor normalization unit configured to receive an original divisor;
• a dividend processing unit configured to receive an original dividend;
• and
• divider logic;
• wherein bits of the original divisor and the original dividend have a first significance relationship;
• wherein the divisor normalization unit is configured to normalize the original divisor by removing sign bits to produce a normalized divisor;
• wherein the dividend processing unit is configured to:
• prescale the original dividend by removing sign bits to produce a prescaled dividend;
• and
• produce an adjusted dividend by adjusting the prescaled dividend so that bits of the normalized divisor and the adjusted dividend maintain the first significance relationship;
• wherein the divider logic is configured to divide the adjusted dividend by the normalized divisor.

A processor comprising:

• a cache;
• an instruction decode unit coupled to receive instructions from the cache;
• and
• a divider unit, wherein the divider unit is configured to:
• receive an original divisor and an original dividend, wherein bits of the original divisor and the original dividend have a first significance relationship;
• normalize the original divisor by removing sign bits to produce a normalized divisor;
• prescale the original dividend by removing sign bits to produce a prescaled dividend;
• and
• produce an adjusted dividend by adjusting the prescaled dividend so that bits of the normalized divisor and the adjusted dividend maintain the first significance relationship;
• and
• divide the adjusted dividend by the normalized divisor.