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US 7,584,233 B2Granted
System and method of counting leading zeros and counting leading ones in a digital signal processor
AssigneeQUALCOMM Incorporated
InventorsChristopher Edward Koob, Jian Liang
Life of this patent
Estimating the term…
Abstract
A system and method is disclosed and includes an execution unit that can be used to count the leading zeros in a data word. During operation, the execution unit can receive a data word that has a width of 2 to the Nth power. Further, the execution unit can sign extend the data word to a temporary data word that has a width of 2 to the Mth power, wherein M is greater than N. The temporary data word can be input to a counter that has a width of 2 to the Mth power and the counter can count the leading zeros within the temporary data word to get a result.
Claims39
A method of processing a data word, the method comprising:
- receiving the data word;
- determining whether the data word has a first width or a second width, the second width greater than the first width;
- after determining that the data word has the first width, sign extending the data word to create a data word having the second width;
- and
- subtracting a value from an interim count of leading data bits of the data word having the second width to determine a final count of leading data bits.
2 more elements
A method comprising:
- using a sixty-four bit logic counter to count zero or more leading zeros within a thirty-two bit data word;
- sign extending the thirty-two bit data word to create a sixty-four bit data word;
- counting the leading zeros within the sixty-four bit data word to obtain an interim result;
- and
- subtracting a fixed value from the interim result, provided the count of the leading zeros is not zero, to obtain a final result.
2 more elements
An instruction execution unit for a digital signal processor, the instruction execution unit, comprising:
- a control module;
- a sign extender coupled to the control module;
- at least one inverter coupled to the control module;
- and
- a sixty-four bit wide bit counter coupled to the control module, wherein the control module includes:
- logic to instruct the sixty-four bit wide bit counter to count leading zeros within one or more thirty-two bit data words received at the instruction execution unit;
- logic to instruct the sixty-four bit wide bit counter to count leading zeros within one or more sixty-four bit data words received at the instruction execution unit;
- logic to control the sign extender to sign extend the one or more thirty-two bit data words to create a temporary sixty-four bit data word;
- logic to instruct the sixty-four bit wide bit counter to count the leading zeros within the temporary sixty-four bit data word to obtain an interim leading zeros count;
- and
- logic to subtract a fixed value from the interim leading zeros count, provided the interim leading zeros count is not zero, to obtain a final leading zeros count.
8 more elements
A portable communication device, comprising:
- a digital signal processor, wherein the digital signal processor comprises:
- a memory;
- a sequencer responsive to the memory;
- a register file coupled to the memory;
- an instruction execution unit responsive to the sequencer, wherein the instruction execution unit comprises:
- a control module;
- a sign extender coupled to the control module;
- an inverter coupled to the control module;
- and
- a sixty-four bit wide bit counter coupled to the control module, wherein the control module includes:
- logic to control the sixty-four bit wide bit counter to count leading zeros within one or more thirty-two bit data words;
- and
- logic to control the sixty-four bit wide bit counter to count leading zeros within one or more sixty-four bit data words;
- a baseband processor coupled to the digital signal processor;
- a coder/decoder (CODEC) coupled to the baseband processor;
- a radio frequency (RF) transceiver coupled to the baseband processor;
- and
- an antenna coupled to the RF transceiver.
15 more elements
A processor device, comprising:
- means for receiving a thirty-two bit data word;
- means for sign extending the thirty-two bit data word to create a temporary sixty-four bit data word;
- means for counting the leading zeros within the temporary sixty-four bit data word to obtain an interim leading zeros count;
- and
- means for subtracting a value from the interim leading zeros count, provided the count is not zero, to obtain a final leading zeros count.
2 more elements
A processor device, comprising:
- means for receiving a thirty-two bit data word;
- means for sign extending the thirty-two bit data word to create a temporary sixty-four bit data word;
- means for inverting the temporary sixty-four bit data word to create an inverted temporary sixty-four bit data word;
- means for counting the leading zeros within the temporary sixty-four bit data word to obtain an interim leading ones count;
- and
- means for subtracting a value from the interim leading ones count, provided the count is not zero, to obtain a final leading ones count.
3 more elements
A method of processing a data word, comprising:
- receiving a data word having a width of 2 to the Nth power;
- sign extending the data word to a temporary data word having a width of 2 to the Mth power;
- inputting the temporary data word to a counter having a width of 2 to the Mth power;
- counting the leading zeros within the temporary data word to produce a temporary result;
- and
- subtracting a value equal to 2 to the Mth power minus 2 to the Nth power from the temporary result to determine a count.
3 more elements
A processor device, comprising:
- means for receiving a data word having a width of 2 to the Nth power;
- means for sign extending the data word to a temporary data word having a width of 2 to the Mth power;
- means for inputting the temporary data word to a counter having a width of 2 to the Mth power;
- means for counting the leading zeros within the temporary data word to produce a temporary result;
- and
- means for subtracting a value equal to 2 to the Mth power minus 2 to the Nth power from the temporary result to produce a count.
3 more elements
An audio file player, comprising:
- a digital signal processor;
- an audio coder/decoder (CODEC) coupled to the digital signal processor;
- a multimedia card coupled to the digital signal processor;
- a universal serial bus (USB) port coupled to the digital signal processor;
- and
- wherein the digital signal processor includes:
- a memory;
- a sequencer responsive to the memory;
- a register file coupled to the memory;
- an instruction execution unit responsive to the sequencer, wherein the instruction execution unit comprises:
- a control module;
- a sign extender coupled to the control module;
- an inverter coupled to the control module;
- and
- a sixty-four bit wide bit counter coupled to the control module, wherein the control module includes:
- logic to control the sixty-four bit wide bit counter to count leading zeros within one or more thirty-two bit data words;
- and
- logic to control the sixty-four bit wide bit counter to count leading zeros within one or more sixty-four bit data words.
15 more elements
Dependencies are inferred from the claim text.