MAC controlled sleep mode/wake-up mode with staged wake-up for power management
AssigneeBroadcom Corporation
InventorsMark D. Matson, Bruce E. Edwards
Life of this patent
Estimating the term…
Abstract
A power management scheme for a wireless communications device processor substantially implemented on a single CMOS integrated circuit is described. By incorporating controls for sleep and wake-up mode transitions in the processor's control logic, improved power savings with reduced latency is provided, obviating the need for hardware-focused solutions with elaborate signaling mechanisms. A fully integrated power management with staged wake-up operations controlled by the MAC solution consumes less power than the conventional wireless LAN solutions in standby mode.
Claims20
A data processor for use in a wireless communication device, comprising:
- a processing unit;
- an instruction pipeline circuit;
- at least one processing module;
- a timer for generating a time-out interval;
- and
- power control logic for detecting a sleep instruction and placing the processing unit, instruction pipeline circuit and at least one processing module in a low-power state, where the power control logic is operative in response to a wake-up signal to reactivate the instruction pipeline circuit, and consequently at least one processing module only to the extent required by the wake-up signal.
An article of manufacture having at least one computer readable medium encoded with a computer program comprising executable instructions and data which, when executed by at least one processing device, cause the at least one processing device to:
- detect a sleep instruction for the processing device;
- specify one or more wake-up conditions and a time-out interval;
- power down an instruction pipeline and one or more processor modules;
- reactivate the instruction pipeline upon detection of a wake-up signal corresponding to either a wake-up condition or the time-out interval, and
- process one or more instructions in the instruction pipeline to reactivate any of the one or more processor modules required to respond to a detected wake-up condition.
A method for managing power in a communications processor by selectively removing one or more processor modules from a standby mode, comprising:
- storing one or more wake-up conditions and a time-out interval in a register;
- receiving a processor sleep instruction;
- executing any pending instructions received by the processor before the sleep instruction;
- powering down the one or more processor modules, where one of the processor modules comprises an instruction pipeline circuit;
- receiving a processor wake-up signal corresponding to one of said wake-up conditions or said time-out interval;
- powering up only the processor modules required to respond to the detected processor wake-up signal.
Dependencies are inferred from the claim text.