Wireless communication system and method using clock swapping during image rejection calibration

A radio frequency receiver comprising:

• a radio frequency (RF) input;
• a mixer, coupled to the RF input;
• a plurality of receiver stages coupled to the mixer, one of the stages being a digital signal processor (DSP);
• a test signal generator, coupled to the mixer, that supplies the mixer with a test signal exhibiting a predetermined frequency, when the receiver is in a test mode;
• a divider, coupled to the test signal generator, that divides the test signal to provide a first clock signal exhibiting a first frequency to the receiver stages, when the receiver is in the test mode, the DSP determining image correction information relating to errors caused by the receiver stages while in the test mode;
• and
• a main reference clock, coupled to the receiver stages, that supplies the receiver stages with a second clock signal exhibiting a second frequency when the receiver is in a normal mode, a receive signal being supplied to the mixer instead of the test signal when the receiver is in the normal mode thus generating a mixed receive signal, the DSP correcting the mixed receive signal with the image correction information to suppress image signals therein when the receiver is in the normal mode.

An integrated circuit comprising:

• a substrate;
• a radio frequency (RF) input;
• a mixer, coupled to the RF input;
• a plurality of receiver stages coupled to the mixer, one of the stages being a digital signal processor (DSP);
• a test signal generator, coupled to the mixer, that supplies the mixer with a test signal exhibiting a predetermined frequency, when the receiver is in a test mode;
• a divider, coupled to the test signal generator, that divides the test signal to provide a first clock signal exhibiting a first frequency to the receiver stages, when the receiver is in the test mode, the DSP determining image correction information relating to errors caused by the receiver stages while in the test mode;
• and
• a main reference clock, coupled to the receiver stages, that supplies the receiver stages with a second clock signal exhibiting a second frequency when the receiver is in a normal mode, a receive signal being supplied to the mixer instead of the test signal when the receiver is in the normal mode thus generating a mixed receive signal, the DSP correcting the mixed receive signal with the image correction information to suppress image signals therein when the receiver is in the normal mode;
• the RF input, the mixer, the plurality of receiver stages, the test signal generator, the divider and the main reference clock all being situated on the substrate.