Synchronizing clocks across a communication link

A slave synchronization system for use in a communication link to adjust a controllable local slave clock to match a received synchronization signal, the slave synchronization system comprising:

• a receiver module configured to receive transmissions;
• a slave clock module configured to provide the controllable local slave clock output at a slave clock rate and having a slave clock period;
• a slave-side modem module configured to demodulate signals from the receiver module;
• a slave-side expected preamble module configured to provide an expected synchronization data signal comparable to the received synchronization signals;
• a slave-side counter module configured to determine an expected receipt time for each synchronization signal by counting an expected number of clock cycles of the slave clock;
• a burst correlator module configured to compare signals received from the slave-side modem with the expected synchronization data signal from the slave-side expected preamble module to determine the synchronization signal receipt time in terms of slave clock periods, the burst correlator module including a correlator submodule configured to provide a first correlation digital output at a sample rate of n times the slave clock rate, the first correlation digital output producing an identifiable best correlation sample indicating a sample time reflective of a closest match between the synchronization signal and the expected synchronization signal, an interpolator submodule configured to evaluate samples of the correlation digital output around the best correlation sample and to provide a plurality of interpolator outputs reflecting a synchronization signal receipt time at an interpolator resolution which is less than a sample period of 1/n slave clock periods, and a slave clock error generator submodule to provide a slave clock error signal from a difference between the determined synchronization signal receipt time and the expected synchronization signal receipt time;
• and
• a loop filter module configured to filter the slave clock error signal and apply the filtered signal to control the slave clock.

Apparatus for adjusting a plurality of clocks at a communication station receiving data from a transmitting communication station, the apparatus comprising:

• a modem which receives a signal from the transmitting communication station, including a synchronization signal timing sensor, and a data discriminator which determines data in the received signal including received clock compare data;
• a noncommon clock subsystem including a controllable noncommon clock, and a noncommon clock controller which adjusts a frequency of the noncommon clock on the basis of a difference between an arrival time of the synchronization signal sensed by the timing sensor and an expected arrival time of the synchronization signal predicted by the time required for a predetermined number of cycles of the noncommon clock;
• and
• a secondary clock subsystem, including a controllable secondary clock, a compare counter to determine secondary clock compare data reflecting comparison between a frequency of the secondary clock and the frequency of the noncommon clock, and a clock controller to change the frequency of the secondary clock in response to a difference between the determined secondary clock compare data and the received clock compare data.

Apparatus for synchronizing clocks across a communication link having a first side and a second side opposite the first side, the apparatus comprising:

• a first modem which sends a synchronization signal from the first side of the link to the second side of the link periodically at a period defined by a predetermined number of cycles of a first noncommon clock;
• a second modem at the second side of the link which receives the periodic synchronization signal from the first side of the link;
• a second noncommon clock circuit on the second side of the link, including a counter which counts a predetermined number of cycles of the second noncommon clock to indicate an expected time of arrival for the synchronization signal, a timing comparator which determines a difference between an actual time of arrival of the periodic synchronization signal received by the second modem and the expected time of arrival, and a noncommon clock error signal circuit which converts the time of arrival difference to a signal controlling a frequency of the second noncommon clock;
• a master clock subsystem on a master side of the link, including a master clock, and a master clock compare counter to determine master clock compare data reflecting comparison of a frequency of the master clock and a frequency of either (i) the first noncommon clock or (ii) the second noncommon clock, whichever is local to the master side of the link;
• and
• a slave clock subsystem on a slave side of the link opposite the master side, including a controllable slave clock, a slave clock compare counter to determine slave clock compare data reflecting comparison between a frequency of the slave clock and a frequency of either (a) the second noncommon clock, or (b) the first noncommon clock, whichever is local to the slave side of the link, and a slave clock controller to change the frequency of the slave clock in response to a difference between the determined slave clock compare data and master clock compare data.