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US 7,583,559 B2Granted
Two transistor wordline decoder output driver
AssigneeIntel Corporation
InventorsHari Giduturi, Mark Bauer, Hernan A. Castro
Life of this patent
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Abstract
A wordline decoder scheme for a memory device is generally described. In one example, a memory device includes a distributed logical NOR gate to decode addressing signals to generate wordline selection signals within a block of memory wherein the distributed logical NOR gate comprises a wordline decoder output driver, the wordline decoder output driver comprising two transistors coupled with a wordline signal.
Claims7
An apparatus, comprising:
- a distributed logical NOR gate to decode addressing signals to generate wordline selection signals within a block of memory wherein the distributed logical NOR gate comprises a wordline decoder output driver, the wordline decoder output driver comprising two transistors coupled with a wordline signal, the wordline decoder output driver further comprising
- a first p-type transistor having a source coupled with a drain of a second p-type bank enable transistor and a gate coupled to receive a row decode signal;
- and
- a first n-type transistor having a drain coupled with the drain of the first p-type transistor and a gate coupled to receive the row decode signal,
- the first p-type transistor, the second p-type bank enable transistor, and the first n-type transistor being triple-well transistors;
- and
- a second n-type transistor to discharge a parasitic node upon deselection, the second n-type transistor having a source coupled with the source of a first p-type transistor in the wordline decoder output driver and a gate coupled with a gate of a second p-type bank enable transistor, the second n-type transistor being a triple-well transistor and being provided once for each bank of wordlines.
4 more elements
A systems, comprising:
- an omnidirectional antenna;
- a processor coupled to communicate via the antenna;
- and
- a memory device coupled with the processor, the memory device comprising a wordline decoder output driver having a first p-type transistor and a first n-type transistor coupled with a wordline signal, wherein the first p-type transistor comprises a source coupled with a drain of a second p-type bank enable transistor and a gate coupled to receive a row decode signal, and wherein the first n-type transistor comprises a drain coupled with the drain of the first p-type transistor and a gate coupled to receive the row decode signal, the first p-type transistor, the second p-type bank enable transistor, and the first n-type transistor being triple-well transistors, the wordline decoder output driver further comprising a second n-type transistor to discharge a parasitic node upon deselection, the second n-type transistor having a source coupled with the source of the first p-type transistor and a gate coupled with a gate of the second p-type bank enable transistor, the second n-type transistor being provided to discharge the parasitic node upon deselection prior to an access, and the second n-type transistor being a triple-well transistor and being provided once for each bank of wordlines.
1 more element
Dependencies are inferred from the claim text.