Multi-port memory device with serial input/output interface and control method thereof
AssigneeHynix Semiconductor Inc.
InventorChang-Ho Do
Life of this patent
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Abstract
A semiconductor memory device includes plural ports for transmitting an input data serial-interfaced with an external device into a global data bus, plural banks for parallel-interfacing with the plural ports through the global data bus, plural input signal transmission blocks, responsive to a mode register enable signal, for transmitting an input signal parallel-interfaced with the external device into the global data bus, and a mode register set for determining one of a data access mode and a test mode based on the input signal inputted through the global data bus.
Claims23
A semiconductor memory device, comprising:
- a plurality of ports for transmitting input data into a global data bus;
- a plurality of banks for parallel-interfacing with the plurality of ports through the global data bus;
- a plurality of input signal transmission blocks, responsive to a mode register enable signal, for transmitting an input signal into the global data bus;
- and
- a mode register set for determining one of a data access mode and a test mode based on the input signal inputted into the global data bus.
A method for supporting serial and parallel interfaces of semiconductor memory device with an external device, wherein the semiconductor memory device includes a plurality of ports for transmitting an input data into a global data bus and a plurality of banks for parallel-interfacing with the plurality of ports through the global data bus, comprising:
- transmitting an in put signal into the global data bus in response to a mode register enable signal;
- and
- determining one of a data access mode and a test mode based on the input signal inputted through the global data bus in response to the mode register enable signal.
A method for supporting serial and parallel interfaces of semiconductor memory device with an external device, comprising:
- transmitting an input signal into the global data bus in response to a mode register enable signal;
- determining one of a data access mode and a test mode based on the input signal inputted through the global data bus in response to the mode register enable signal;
- serially interfacing with the external device if the data access mode is performed;
- and
- parallel interfacing with the external device if the test mode is performed.
Dependencies are inferred from the claim text.