Method and system for providing independent bank refresh for volatile memories

#1. Field

#The present disclosure relates generally to memory devices, and more specifically, to methods and systems for providing independent bank refresh for volatile memories.

#2. Background

#Aspects of the present invention are illustrated by way of example, and not by way of limitation, in the accompanying drawings, wherein:

#FIG. 1 is a simplified block diagram illustrating an arrangement that can be used to practice the independent refresh method according to the present disclosure; and

#FIG. 2 is a simplified block diagram illustrating a volatile memory that can be used to practice the independent refresh method according to the present disclosure.

#The detailed description set forth below in connection with the appended drawings is intended as a description of various embodiments of the present invention and is not intended to represent the only embodiments in which the present invention may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring the concepts of the present invention.

#Various embodiments of a memory system will now be described. In one embodiment, an independent refresh method is provided which improves data availability in a memory during refresh operations. FIG. 1 shows an arrangement 100 that can be used to practice the independent refresh method. As shown in FIG. 1 , the independent refresh method may be practiced with a volatile memory 110 and a controller 120 configured to control the volatile memory. The volatile memory 110 can be, for example, a DRAM (dynamic random access memory), a SDRAM (synchronous DRAM), and various other types of DRAM, etc. Based on the disclosure and teachings provided herein, a person of ordinary skill in the art will appreciate how to practice the present disclosure with other types of memories which require refresh operations. In one implementation, the independent refresh method is effected via control logic or a processor which controls the memory controller 120 and the volatile memory 110. The memory controller 120 may be to post an independent refresh to a specific bank 130 to the volatile memory 110. It should be understood that the control logic or processor may be implemented as an independent module or integrated as part of another component, such as, the memory controller 120.

#FIG. 2 further shows one embodiment of the volatile memory 110 that can be used to practice the independent refresh method. The volatile memory 110 may further include a bank address latch 200, a refresh trigger 230, a number of refresh row counters 210a-d and a number of banks 220a-d. The bank address latch 200 is used to store the target bank address for the specific bank that is to be refreshed. The banks 220a-d are each associated with their corresponding refresh row counters 210a-d. The initial values for the refresh row counters 210a-d are initialized upon power-up or reset. For example, the refresh row counter 210a is associated with the bank 220a. The refresh row counters 210a-d are used to maintain target row addresses for rows that are to be refreshed in the respective banks 220a-d. The target row addresses stored in the refresh row counters 210a-d are independent of each other. The refresh trigger 230 is used to control the bank address latch 200 during self-refresh mode, as will be further described below. The refresh trigger 230 can be, for example, a clock or other timing mechanisms.