Power management control and controlling memory refresh operations
AssigneeMicron Technology, Inc.
InventorDean A. Klein
Life of this patent
Estimating the term…
Abstract
A memory devices provide signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by Oring, to provide a refresh complete signal to a power management controller. Dynamic factors can affect the refresh operation and the memory may be refreshed without restoring the entire system to a high power state. The time required to perform a refresh operation can be determined dynamically, allowing the system to be returned to a low power state as soon as refresh is complete. Ambient temperatures can be monitored to dynamically determine when to perform a refresh operation.
Claims69
A memory device, comprising:
- a memory array;
- a refresh circuit for controlling a refresh operation of the memory array, for monitoring said memory array, and for indicating when said refresh operation is complete based on said monitoring of said memory array;
- and
- a control logic circuit that controls an operation of said memory array, said control logic circuit providing a first control signal to said refresh circuit, said refresh circuit providing a second control signal to said control logic circuit.
A memory system, comprising:
- a set of memory devices, each comprising:
- a memory array;
- a refresh circuit coupled to said memory array for controlling a refresh operation of said memory array and for providing a refresh complete signal indicating when said refresh operation is complete;
- and
- a combining circuit for combining the refresh complete signals from the memory devices to obtain a combined refresh complete signal.
A memory system, comprising:
- a power management circuit, comprising:
- a micro-controller for controlling an operation of said power management circuit;
- an input-output port circuit for inputting signals from and providing signals to other circuits;
- a set of memory devices, each comprising:
- a memory array;
- a refresh circuit coupled to said memory array for controlling a refresh operation of said memory array and for providing a refresh complete signal indicating when said refresh operation is complete;
- and
- a combining circuit for combining the refresh complete signals from the memory devices to obtain a combined refresh complete signal, said combining circuit includes a wired-or circuit;
- wherein said power management circuit adapted to receive the combined refresh complete signal through the input-output port and, partially in response, for controlling power provided to each of said memory devices, said power management circuit being coupled to each of said memory devices.
A memory system, comprising:
- a set of memory devices;
- a power management circuit for controlling power provided to each of said memory devices, said power management circuit being coupled to each of said memory devices;
- the power management circuit comprising:
- a micro-controller for controlling an operation of said power management circuit;
- and
- a temperature integration circuit for incorporating temperature into a refresh operation.
A memory system, comprising:
- a memory array;
- a refresh circuit for controlling a refresh operation of the memory array and for indicating when said refresh operation is complete;
- and
- a power management circuit, comprising:
- a micro-controller for controlling an operation of said power management circuit;
- an input-output port circuit for inputting signals from and providing signals to other circuits;
- and
- a temperature integration circuit for incorporating temperature into a refresh operation.
A memory device comprising:
- refresh circuitry for controlling a refresh operation in a memory device;
- and
- a sensor for sensing an environmental condition of the memory device;
- wherein said refresh circuitry is adapted to initiate the refresh operation partially in response to the environmental condition sensed by the sensor, said refresh circuitry adapted to indicate when said refresh operation is complete.
A method of refreshing memory, comprising:
- performing a burst self-refresh operation on a memory array;
- and
- providing a refresh complete signal when said burst self-refresh operation has been completed.
The method of claim of 42, further comprising the step of determining a pre-refresh mode of said memory array before performing said burst self-refresh operation.
The method of claim of 43, wherein said pre-refresh mode is either a first or second mode.
The method of claim of 44, wherein said first mode is a low-power mode.
The method of claim of 44, wherein said second mode is a higher-power mode.
The method of claim of 44, further comprising the step of changing said memory array to said second mode before said performing said refresh operation, if said pre-refresh mode is said first mode.
The method of claim of 42, further comprising the steps of:
- measuring an ambient temperature;
- and
- initiating said refresh operation at a certain rate if said ambient temperature is in a first set of refresh temperature values.
The method of claim of 49, wherein said first set of refresh temperature values are pre-determined temperatures.
The method of claim of 49, further comprising the step of integrating said ambient temperature after measuring said ambient temperature.
The method of claim of 49, wherein said first set of refresh temperature values are pre-determined values based on integrated temperature values.
A method of refreshing memory devices, each with a memory array the method comprising:
- performing a refresh operation in a subset of the memory devices;
- providing a refresh complete signal from each memory device in the subset when the memory device completes the refresh operation;
- and
- combining the refresh signals to obtain a combined refresh complete signal.
An integrated circuit, comprising:
- a memory device, comprising:
- a memory array;
- a refresh circuit for controlling a refresh operation of the memory array, for monitoring said memory array, and for indicating when said refresh operation is complete based on said monitoring of said memory array;
- and
- a control logic circuit for controlling an operation of said memory array, said control logic circuit adapted to provide a first control signal to said refresh circuit, said refresh circuit provide a second control signal to said control logic circuit.
An integrated circuit, comprising:
- a memory device comprising:
- refresh circuitry for controlling a refresh operation in a memory device;
- and
- a sensor for sensing an environmental condition of the memory device;
- wherein said refresh circuitry adapted to initiate the refresh operation partially in response to the environmental condition sensed by the sensor, said refresh circuitry adapted to indicate when said refresh operation is complete.
A processor system, comprising:
- a processor, and
- a memory device, comprising:
- a memory array;
- a refresh circuit for controlling a refresh operation of the memory array, for monitoring said memory array, and for indicating when said refresh operation is complete based on said monitoring of said memory array;
- and
- a control logic circuit for controlling an operation of said memory array and for providing a first control signal to said refresh circuit, said refresh circuit providing and a second control signal to said control logic circuit.
A processor system, comprising:
- a processor, and
- a memory device comprising:
- refresh circuitry for controlling a refresh operation in a memory device;
- and
- a sensor for sensing an environmental condition of the memory device;
- wherein said refresh circuitry adapted to initiate the refresh operation partially in response to the environmental condition sensed by the sensor,
- said refresh circuitry adapted to indicate when said refresh operation is complete.
Dependencies are inferred from the claim text.