Semiconductor memory device

A semiconductor memory device, comprising:

• a memory cell array in which memory cells are provided in matrix form;
• a plurality of word lines respectively connected to a plurality of rows of the memory cell array;
• a plurality of bit line pairs respectively connected to the plurality of columns of the memory cell array;
• a word driver that drives a word line selected from the plurality of word lines according to a row address during a memory access operation;
• and
• a plurality of sense amplifier portions that are arranged in order and supply a bit line potential to the plurality of bit line pairs during a memory access operation;
• wherein each of the plurality of sense amplifier portions comprises:
• a bit line potential supply line to which the bit line potential is supplied;
• a transistor that is connected to the bit line potential supply line and is turned on when a signal level of a precharge signal is in an active state, thereby to supply the bit line potential to the bit line pair in a corresponding column of the memory cell array;
• and
• a gate electrode for supplying the precharge signal to a gate of the transistor;
• wherein the gate electrode of the plurality of sense amplifier portions is provided as one piece as a whole and extends in a direction parallel to a row direction in the memory cell array, and
• wherein a gate-electrode portion is ring-shaped, said gate electrode portion being a connected portion between the gate electrode in a k-th sense amplifier portion among the plurality of sense amplifier portions and the gate electrode in a (k+1)-th sense amplifier portion, k being an odd number.