Semiconductor memory apparatus for allocating different read/write operating time to every bank
AssigneeHynix Semiconductor Inc.
InventorKhil-Ohk Kang
Life of this patent
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Abstract
A semiconductor memory apparatus includes an active signal generation unit that generates a plurality of active signals having different enable timings in response to a refresh signal, a precharge signal generation unit that delays at least one of the active signals to generate at least one precharge signal for enabling at least two equalizer signals at the same time, and a sense amplifier driver control unit that generates the plurality of equalizer signals for controlling individual sense amplifier drivers in response to the plurality of active signals and the precharge signal.
Claims12
A semiconductor memory apparatus comprising:
- an active signal generation unit that generates a plurality of active signals having different enable timings in response to a refresh signal;
- a precharge signal generation unit that delays at least one active signal to generate at least one precharge signal for enabling at least two equalizer signals at the same time;
- and
- a sense amplifier driver control unit that generates the plurality of equalizer signals for controlling individual sense amplifier drivers in response to the plurality of active signals and the precharge signal.
A semiconductor memory apparatus comprising:
- an active signal generation unit that generates a plurality of active signals having different enable timings in response to a refresh signal;
- a precharge signal generation unit that delays one active signal having a latest enable timing to generate a precharge signal for enabling all equalizer signals;
- and
- a sense amplifier driver control unit that generates the plurality of equalizer signals for controlling individual sense amplifier drivers in response to the plurality of active signals and the precharge signal,
- wherein the precharge signal generation unit includes delay units, a number of which is smaller than a number of active signals.
A semiconductor memory apparatus comprising:
- an active signal generation unit that generates a plurality of active signals having different enable timings in response to a refresh signal;
- a sense amplifier driver control unit that includes a plurality of sense amplifier driver controllers, each of which receives the corresponding active signal and a precharge signal;
- and
- a precharge signal generation unit that includes at least one delay unit for delaying at least one of the active signals and outputting the precharge signal,
- wherein at least one precharge signal is commonly output to at least two sense amplifier driver controllers, and
- a number of delay units is smaller than a number of active signals.
Dependencies are inferred from the claim text.