Apparatus and method of operating an integrated circuit
AssigneeQimonda AG
InventorsStefan Dietrich, Peter Schroegmeier
Life of this patent
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Abstract
The method of operating an integrated circuit including the step of writing to a memory cell, which can assume a first and a second logical state and wherein a change from the second logical state to the first logical state lasts longer than a change from the first logical state to the second logical state, includes reading the logical state of the memory cell, changing, depending on the logical state of the memory cell read, the logical state to the first logical state or retaining the same in the first logical state and, depending on the logical state to be written, changing the logical state to the second logical state or retaining the same in the first logical state.
Claims41
A method of operating an integrated circuit including the step of writing to a memory cell which can assume a first and a second logical state, wherein a change from the second logical state to the first logical state in the memory cell takes a longer time than a change from the first logical state to the second logical state, the method comprising:
- reading a logical state of the memory cell;
- depending on the logical state of the memory cell read, changing the logical state to the first logical state or retaining the same in the first logical state;
- and
- depending on the logical state to be written, changing the logical state to the second logical state or retaining the same in the first logical state.
An integrated circuit comprising:
- a memory cell able to assume a first and a second logical state, wherein a change from the second logical state to the first logical state lasts longer than a change from the first logical state to the second logical state;
- a reading circuit being connectable to the memory cell;
- and
- a control circuit configured to cause a change of the logical state of the memory cell to the first logical state or a retainment of the logical state of the memory cell in the first logical state, depending on the logical state of the memory cell read, and cause a change of the logical state of the memory cell to the second logical state or a retainment of the logical state of the memory cell in the first logical state, depending on the logical state to be written.
An integrated circuit comprising:
- a memory cell able to assume a first and a second logical state, wherein a change from the second logical state to the first logical state lasts longer than a change from the first logical state to the second logical state;
- means for reading the logical state of the memory cell;
- means for changing, depending on the logical state of the memory cell read, the logical state of the memory cell to the first logical state or retaining the same in the first logical state;
- and
- means for changing the logical state of the memory cell to the second logical state or retaining the same in the first logical state, depending on the logical state to be written.
An integrated circuit comprising:
- a memory cell able to assume a first and a second logical state, wherein a change from the second logical state to the first logical state lasts longer than a change from the first logical state to the second logical state;
- a buffer;
- a switch connected between the memory cell and the buffer;
- a reading circuit;
- a resetting circuit;
- and
- a control circuit configured to cause opening the switch to disconnect the memory cell from the buffer, to read a buffered state from the buffer, to instruct the resetting circuit to change the logical state of the memory cell to the first logical state or retain the same in the first logical state, depending on the buffered state read, to cause changing the logical state of the memory cell to the second logical state or retaining the same in the first logical state, depending on the logical state to be written, and to cause closing the switch to connect the memory cell and the buffer.
A data processing system comprising at least one integrated circuit, the integrated circuit comprising:
- a memory cell able to assume a first and a second logical state, wherein a change from the second logical state to the first logical state lasts longer than a change from the first logical state to the second logical state;
- a reading circuit being connectable to the memory cell;
- and
- a control circuit configured to cause a change of the logical state of the memory cell to the first logical state or a retainment of the logical state of the memory cell in the first logical state, depending on the logical state of the memory cell read, and cause a change of the logical state of the memory cell to the second logical state or a retainment of the logical state of the memory cell in the first logical state, depending on the logical state to be written.
Dependencies are inferred from the claim text.