Semiconductor memory and read method of the same
AssigneeKabushiki Kaisha Toshiba
InventorsMutsuo Morikado, Tomoki Higashi
Life of this patent
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Abstract
A semiconductor memory including a memory cell which is a MOSFET formed on an SOI substrate. The memory cell has a gate electrode connected to a word line, a drain region connected to a bit line, and a grounded source region. An operation of reading out data written in the memory cell is performed under a biasing condition by which a relationship Vd>Vg−Vth0 holds between a gate voltage Vg to be applied to said gate electrode, a drain voltage Vd to be applied to said drain region, a threshold voltage Vth1 of said MOSFET when a predetermined amount of holes are stored in a body region of the memory cell, and a threshold voltage Vth0 of said MOSFET when holes whose amount is smaller than the predetermined amount are stored in the body region.
Claims17
A semiconductor memory comprising a memory cell which is a MOSFET formed on an SOL substrate and having a gate electrode connected to a word line, a drain region connected to a bit line, and a grounded source region,
- wherein an operation of reading out data written in said memory cell is performed under a biasing condition by which relationships Vd>Vg−Vth0 and Vth1 Vg≦Vth0 holds between a gate voltage Vg to be applied to said gate electrode, a drain voltage Vd to be applied to said drain region, a threshold voltage Vth1 of said MOSFET when a predetermined amount of holes are stored in a body region of said memory cell, and a threshold voltage Vth0 of said MOSFET when holes whose amount is smaller than the predetermined amount are stored in said body region.
A semiconductor memory, comprising;
- a cell array having a plurality of memory cells at intersections of a plurality of word lines provided in row direction and a plurality of bit lines provided in column direction;
- a column decoder selecting the bit lines;
- a row decoder selecting the word lines;
- and
- a sense amplifier connected to the bit lines and reading out data written in the memory cells,
- wherein each of said memory cells is MOSFET formed on an SOI substrate and having a gate electrode connected to one of said word lines, a drain region connected to one of said bit lines, and a grounded source region,
- wherein an operation of reading out data written in said memory cell is performed under a biasing condition by which a relationship Vd>Vg−Vth0 holds between a gate voltage Vg to be applied to said gate electrode, a drain voltage Vd to be applied to said drain region, a threshold voltage Vth1 of said MOSFET when a predetermined amount of holes are stored in a body region of said memory cell, and a threshold voltage Vth0 of said MOSFET when holes whose amount is smaller than the predetermined amount are stored in said body region.
A read method of a semiconductor memory comprising a memory cell which is a MOSFET formed on an SOI substrate and having a gate electrode connected to a word line, a drain region connected to a bit line, and a grounded source region,
- wherein an operation of reading out data written in said memory cell is performed under a biasing condition by which relationships Vd>Vg−Vth0 and the Vth1≦Vg≦Vth0 holds between a gate voltage Vg to be applied to said gate electrode, a drain voltage Vd to be applied to said drain region, a threshold voltage Vth1 of said MOSFET when a predetermined amount of holes are stored in a body region of said memory cell, and a threshold voltage Vth0 of said MOSFET when holes whose amount is smaller than the predetermined amount are stored in said body region.
Dependencies are inferred from the claim text.