Charge-trapping memory device and methods for its manufacturing and operation
AssigneeQimonda Flash GmbH
InventorTholasampatti Subramanian Sudhindra Prasad
Life of this patent
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Abstract
A method for leveling bit errors in a charge-trapping memory device is included. The memory device has a first and a second sector of memory cells. The first sector is validated by counting a number of bit failures occurring in memory cells of the first sector, the bit failures caused by accessing memory cells of the second sector. Data stored in the first sector is backed up if the validating indicates a likelihood of a forthcoming failure in the first sector.
Claims10
A method for leveling bit errors in a charge-trapping memory device with a first and a second sector of memory cells, the method comprising:
- validating the first sector by counting a number of bit failures occurring in memory cells of the first sector, the bit failures being caused by accessing memory cells of the second sector;
- and
- backing up data stored in the first sector if the validating indicates a likelihood of a forthcoming failure in the first sector.
A memory card device, comprising:
- a charge-trapping memory device comprising:
- at least two sectors, each sector comprising a data area and redundancy area, each area comprising a plurality of non-volatile memory cells, each memory cell including a charge-trapping layer;
- a bit failure detector operationally connected to a first sector and adapted to detect a number of bit failures of the data area of the first sector based on data stored in the corresponding redundancy area, the bit failures being caused by accessing memory cells of a second sector;
- and
- a controller operationally connected to the first sector and the bit failure detector and adapted to copy data stored in the data area of the first sector to another storage location if the number of bit failures is greater than a predefined threshold;
- an interface for connecting the memory card to a host system;
- and
- an interface controller connecting the interface with the charge-trapping memory device and providing the host system with access to data stored therein.
Dependencies are inferred from the claim text.