Edge controlled fast data pattern generator
AssigneeTektronix International Sales GmbH
InventorHisao Takahashi
Life of this patent
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Abstract
Fast data patterns with desired edge positions are provided. A pattern generator (PG) circuit 10 stores and provides data patterns and respective position control data. A delay circuit 16 delays a clock CLK to produce a position control clock according to the position control data. An output flip flop 18 provides the data patterns following to the position control clock. The position of the clock is controlled as an operation reference of the data pattern and, as a result, controls the edge positions of the output data pattern.
Claims5
A data pattern generating method comprising the steps of:
- generating a divided clock signal from the clock signal;
- generating data pattern bits and corresponding position control data in response to the clock signal;
- providing the data pattern bits to an output circuit;
- providing the clock signal to first and second delay circuits;
- alternately providing the corresponding position control data for each data pattern bit to the first and second delay circuits in response to the divided clock signal;
- delaying the clock signals provided to the first and second delay circuits according to the respective position control data provided to the first and second delay circuits to produce respective alternating position control clocks;
- combining the position control clocks from each of the first and second delay circuits to produce a combined position control clock received by the output circuit according to the alternating position control data;
- and
- generating data patterns bits having at least one of a leading edge and a trailing edge position controlled according to the combined position control clock.
A data pattern generator comprising:
- a pattern generator outputting data pattern bits and corresponding position control data in response to a clock signal;
- a divider circuit receiving the clock signal and generating a divided clock signal;
- a demultiplexer receiving the position control data from the pattern generator and the divided clock signal and alternately outputting the position control data to first and second delay circuits in response to the divided clock;
- the first and second delay circuits receiving the clock signal with the first and second delay circuits each generating a position control clock according to the position control data received from the demultiplexer;
- a combining circuit receiving the respective position control clocks from each of the first and second delay circuits and the divided clock and generating a combined position control clock;
- and
- an output circuit receiving the data pattern bits and the combined position control clock and generating data pattern bits having at least one of a leading edge and a trailing edge position controlled according to the combined position control clock.
Dependencies are inferred from the claim text.