Graphics pipeline precise interrupt method and apparatus

A graphics processing unit (“GPU”) having a graphics pipeline that is configured for interrupting a first context and initiating execution of a second context, comprising:

• a plurality of architectural units in the pipeline coupled by a communication path to a command processor in the GPU, wherein the command processor communicates an interrupt signal on the communication path to each of the architectural units;
• a memory logically positioned between each of the architectural units so that data output from a particular architectural unit is stored in the memory before receipt by a next architectural block in the graphics pipeline;
• logic configured to cause each of the plurality of architectural units to discard the contents of the memory logically positioned between prior to each architectural block upon receipt of the interrupt signal on the communication path until a token is reached in the memory associated with the beginning of the second context;
• and
• logic configured to establish a primitive identifier, a tile identifier, and an instance identifier in a context save buffer corresponding to a processing status of the first context at the moment of receipt of the interrupt signal, the primitive identifier defining an interrupted primitive, the tile identifier defining an interrupted tile, and the instance identifier defining a point of interrupt in an interrupted draw command.

A graphics processing unit (“GPU”) having a graphics pipeline configured for interrupting a first context and initiating execution of a second context, comprising:

• a first plurality of pipeline blocks in the graphics pipeline sequentially coupled together with a FIFO memory logically positioned between each pipeline block;
• a communication path coupled to a command processor in the GPU and to each of the first plurality of pipeline blocks and configured to communicate an interrupt signal from the command processor to each of the first plurality of pipeline blocks such that each of the first plurality of pipeline blocks ceases processing data associated with the first context and operates to purge a FIFO memory that supplies data to the pipeline block until reaching a token fence communicated down the graphics pipeline;
• and
• a second plurality of pipeline blocks positioned after the first plurality of pipeline blocks in the graphics pipeline and not coupled to the communication path, wherein the second plurality of pipeline blocks cease processing data associated with the first context and operate to purge a FIFO memory that supplies data to the pipeline block when the token fence is received;
• wherein the command processor may retrieve state register data associated with the first context from the memory for restoring processing of the first context by the graphics pipeline, the state register data including a primitive identifier, a tile identifier, and an instance identifier and corresponding to a processing status of the first context at the moment of receipt of the interrupt signal, the primitive identifier defining an interrupted primitive, the tile identifier defining an interrupted tile, and the instance identifier defining a point of interrupt in an interrupted draw command.