US 7,583,257 B2 · Signal line driving circuit and light emitting device · patentgrep

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Abstract

Variations occur in the characteristics of transistors. The present invention is a signal-line drive circuit comprising first and second current source circuits corresponding to respective plurality of signal lines, a shift register, and n (n is a natural number of one or more) video-signal constant current source s, wherein each of the first and second current source circuits has a capacitance means and a supply means. The capacitance means held in one of the first and second source circuits converts a current including a current supplied from each of the n video-signal constant current source s to voltage in response to a sampling pulse supplied from the shift register and a latch pulse supplied from the exterior; and the supply means held in the other supplies a current responsive to the converted voltage. The values of the currents supplied from the n video-signal constant current source s are set to a proportion of 20:21: . . . :2n.

Claims32

Dependent claims

A signal-line drive circuit comprising:

a shift register;
a video-signal current source;
a circuit for supplying a latch pulse;
a latch circuit comprising:
a first switch electrically connected to the video-signal current source;
a second switch electrically connected to a signal line;
a first logic circuit electrically connected to the shift register, and to the circuit;
a second logic circuit electrically connected to the shift register, and to the circuit;
a first current source circuit having:
a first terminal electrically connected to the first logic circuit;
a second terminal electrically connected to the first switch;
and
a third terminal electrically connected to the second switch;
and
a second current source circuit having:
a fourth terminal electrically connected to the second logic circuit;
a fifth terminal electrically connected to the first switch;
and
a sixth terminal electrically connected to the second switch,
wherein at least one of the first current source circuit and the second current source circuit comprises a thin film transistor, and
wherein an integrated circuit is used to form the video-signal current source.

18 more elements

A signal-line drive circuit comprising:

a shift register;
n video-signal current sources;
a circuit for supplying a latch pulse;
(n×m) latch circuits, each of the (n×m) latch circuits comprising:
a first switch electrically connected to at least one of the n video-signal current sources;
a second switch electrically connected to corresponding one of m signal lines;
a first logic circuit electrically connected to the shift register, and to the circuit;
a second logic circuit electrically connected to the shift register, and to the circuit;
a first current source circuit having:
a first terminal electrically connected to the first logic circuit;
a second terminal electrically connected to the first switch;
and
a third terminal electrically connected to the second switch;
and
a second current source circuit having:
a fourth terminal electrically connected to the second logic circuit;
a fifth terminal electrically connected to the first switch;
and
a sixth terminal electrically connected to the second switch,
wherein each of n and m is a natural number more than 1,
wherein values of currents to be supplied from the n video-signal current sources are set at 20:21:
. . . :2n−1,
wherein at least one of the first current source circuit and the second current source circuit comprises a thin film transistor, and
wherein an integrated circuit is used to form the n video-signal current sources.

21 more elements

A signal-line drive circuit comprising:

a shift register;
a video-signal current source;
a circuit for supplying a latch pulse;
a latch circuit comprising:
a first switch electrically connected to the video-signal current source;
a second switch electrically connected to a signal line;
a first logic circuit electrically connected to the shift register, and to the circuit;
a second logic circuit electrically connected to the shift register, and to the circuit;
a first current source circuit comprising:
a first transistor;
and
a first capacitive element electrically connected between a gate terminal of the first transistor and a source terminal of the first transistor;
and
a second current source circuit comprising:
a second transistor;
and
a second capacitive element electrically connected between a gate terminal of the second transistor and a source terminal of the second transistor,
wherein the gate terminal of the first transistor and a drain terminal of the first transistor are electrically connected via a third switch,
wherein the drain terminal of the first transistor is electrically connected to the first switch, and to the second switch,
wherein the third switch is controlled by an output of the first logic circuit,
wherein the gate terminal of the second transistor and a drain terminal of the second transistor are electrically connected via a fourth switch,
wherein the drain terminal of the second transistor is electrically connected to the first switch, and to the second switch,
wherein the fourth switch is controlled by an output of the second logic circuit,
wherein at least one of the first current source circuit and the second current source circuit comprises a thin film transistor, and
wherein an integrated circuit is used to form the video-signal current source.

22 more elements

A signal-line drive circuit comprising:

a shift register;
n video-signal current sources;
a circuit for supplying a latch pulse;
(n×m) latch circuits, each of the (n×m) latch circuits comprising:
a first switch electrically connected to at least one of the n video-signal current sources;
a second switch electrically connected to corresponding one of m signal lines;
a first logic circuit electrically connected to the shift register, and to the circuit;
a second logic circuit electrically connected to the shift register, and to the circuit;
a first current source circuit comprising:
a first transistor;
and
a first capacitive element electrically connected between a gate terminal of the first transistor and a source terminal of the first transistor;
and
a second current source circuit comprising:
a second transistor;
and
a second capacitive element electrically connected between a gate terminal of the second transistor and a source terminal of the second transistor,
wherein the gate terminal of the first transistor and a drain terminal of the first transistor are electrically connected via a third switch,
wherein the drain terminal of the first transistor is electrically connected to the first switch, and to the second switch,
wherein the third switch is controlled by an output of the first logic circuit,
wherein the gate terminal of the second transistor and a drain terminal of the second transistor are electrically connected via a fourth switch,
wherein the drain terminal of the second transistor is electrically connected to the first switch, and to the second switch,
wherein the fourth switch is controlled by an output of the second logic circuit,
wherein each of n and m is a natural number more than 1,
wherein values of currents to be supplied from the n video-signal current sources are set at 20:21:
. . . :2n−1,
wherein at least one of the first current source circuit and the second current source circuit comprises a thin film transistor, and
wherein an integrated circuit is used to form the n video-signal current sources.

25 more elements

A signal-line drive circuit comprising:

a shift register;
a video-signal current source;
a circuit for supplying a latch pulse;
a latch circuit comprising:
a first switch electrically connected to the video-signal current source;
a second switch electrically connected to a signal line;
a first logic circuit electrically connected to the shift register, and to the circuit;
a second logic circuit electrically connected to the shift register, and to the circuit;
a first current source circuit comprising:
a first transistor;
a second transistor;
and
a first capacitive element electrically connected between a gate terminal of the first transistor and a source terminal of the first transistor, and between a gate terminal of the second transistor and a source terminal of the second transistor;
and
a second current source circuit comprising:
a third transistor;
a fourth transistor;
and
a second capacitive element electrically connected between a gate terminal of the third transistor and a source terminal of the third transistor, and between a gate terminal of the fourth transistor and a source terminal of the fourth transistor,
wherein the gate terminal of the first transistor and a drain terminal of the first transistor are electrically connected via a third switch,
wherein the drain terminal of the first transistor is electrically connected to the first switch,
wherein a drain terminal of the second transistor is electrically connected to the second switch,
wherein the third switch is controlled by an output of the first logic circuit,
wherein the gate terminal of the third transistor and a drain terminal of the third transistor are electrically connected via a fourth switch,
wherein the drain terminal of the third transistor is electrically connected to the first switch,
wherein a drain terminal of the fourth transistor is electrically connected to the second switch,
wherein the fourth switch is controlled by an output of the second logic circuit,
wherein at least one of the first current source circuit and the second current source circuit comprises a thin film transistor, and
wherein an integrated circuit is used to form the video-signal current source.

26 more elements

A signal-line drive circuit comprising:

a shift register;
n video -signal current sources;
a circuit for supplying a latch pulse;
(n×m) latch circuits, each of the (n×m) latch circuits comprising:
a first switch electrically connected to at least one of the n video-signal current sources;
a second switch electrically connected to corresponding one of m signal lines;
a first logic circuit electrically connected to the shift register, and to the circuit;
a second logic circuit electrically connected to the shift register, and to the circuit;
a first current source circuit comprising:
a first transistor;
a second transistor;
and
a first capacitive element electrically connected between a gate terminal of the first transistor and a source terminal of the first transistor, and between a gate terminal of the second transistor and a source terminal of the second transistor;
and
a second current source circuit comprising:
a third transistor;
a fourth transistor;
and
a second capacitive element electrically connected between a gate terminal of the third transistor and a source terminal of the third transistor, and between a gate terminal of the fourth transistor and a source terminal of the fourth transistor,
wherein the first capacitive element and a drain terminal of the first transistor are electrically connected via a third switch,
wherein the drain terminal of the first transistor is electrically connected to the first switch,
wherein a drain terminal of the second transistor is electrically connected to the second switch,
wherein the third switch is controlled by an output of the first logic circuit,
wherein the second capacitive element and a drain terminal of the third transistor are electrically connected via a fourth switch,
wherein the drain terminal of the third transistor is electrically connected to the first switch,
wherein a drain terminal of the fourth transistor is electrically connected to the second switch,
wherein the fourth switch is controlled by an output of the second logic circuit,
wherein each of n and m is a natural number more than 1,
wherein values of currents to be supplied from the n video-signal current sources are set at 20:21:
. . . :2n−1,
wherein at least one of the first current source circuit and the second current source circuit comprises a thin film transistor, and
wherein an integrated circuit is used to form the n video-signal current sources.

29 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/221,770Filed 9 Sep 2005 · division
Priority: JP 2001-33591831 Oct 2001
Published: US 2006/0028413 A19 Feb 2006
Granted: 1 Sep 2009
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

Family

Application10/283,368Parent of this division · filed 30 Oct 2002
US 2006/0028413 A1Pre-grant publication · published 9 Feb 2006
US 6,963,336 B2Parent of this division
US 2004/0085270 A1Published application
US 7,583,257 B2This patent

From the US filing history. Foreign family members aren’t listed.

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