Method of controlling pipeline analog-to-digital converter and pipeline analog-to-digital converter implementing the same

A method of controlling a pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA), the method comprising the steps of:

• (a) applying an analog input signal to a residual signal generator and an ADC included in a first stage by being triggered by a QS signal within a first Q2 clock pulse;
• (b) sampling, at the residual signal generator, the analog input signal by being triggered by the QS signal within the first Q2 clock pulse;
• (c) after a delay time of a preamp, determining, at a latch of the ADC, a digital code corresponding to the analog input signal using an output value of the preamp by being triggered by a QL signal within the first Q2 clock pulse;
• and
• (d) generating, at the residual signal generator, a residual signal using the digital code in response to a Q1 clock pulse subsequent to the first Q2 clock pulse.

A pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA) comprising a plurality of stages, wherein a first stage comprises:

• a preamp for receiving an analog input signal by being triggered by a QS signal within a first Q2 clock pulse and amplifying and outputting the analog input signal;
• a latch for receiving the output value of the preamp and determining a digital code corresponding to the analog input signal using the output value of the preamp by being triggered by a QL signal within the first Q2 clock pulse;
• and
• a residual signal generator for sampling the analog input signal by being triggered by a QS signal within the first Q2 clock pulse ahead of a point in time when the latch receives the output value of the preamp by a preamp delay time, and generating a residual signal using the digital code.