Logic circuit
AssigneeKabushiki Kaisha Toshiba
InventorMasahiko Motoyama
Life of this patent
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Abstract
A logic circuit that executes a prescribed arithmetic processing includes a decoder that converts one or more binary input data into a first plurality of bit data of a constant hamming weight regardless of a hamming weight of the input data, an interconnect network that is connected to the decoder, changes a bit pattern of the first plurality of bit data and generates a second plurality of bit data, according to receiving the first plurality of bit data converted according to the decoder, and substituting a bit position of the received first plurality of bit data for the purpose of the prescribed arithmetic operation, and an encoder connected to the interconnect network and converts the second plurality of bit data generated in the interconnect network into one or more binary output data.
Claims20
A logic circuit that executes a prescribed arithmetic operation and comprises:
- a decoder that converts one or more binary input data into a first plurality of bit data of a constant hamming weight regardless of a hamming weight of said input data;
- an interconnect network that is connected to said decoder, changes a bit pattern of said first plurality of bit data and generates a second plurality of bit data, by receiving said first plurality of bit data converted by said decoder, and substituting a bit position of received said first plurality of bit data for the purpose of said prescribed arithmetic operation;
- and
- an encoder connected to said interconnect network and converts said second plurality of bit data generated in said interconnect network into one or more binary output data.
A logic circuit that executes a prescribed arithmetic operation and comprises:
- a plurality of decoders that convert one or more binary input data into a first plurality of bit data of a constant hamming weight regardless of a hamming weight of said input data;
- a plurality of interconnect networks that are connected to said plurality of decoders, substitutes a bit position of said first plurality of bit data for the purpose of said prescribed arithmetic operation and generate a second plurality of bit data, by receiving said first plurality of bit data converted by said connected decoder, and changing connection of a plurality of interconnect corresponding to each of received said first plurality of bit data;
- and a plurality of encoders that are connected to said plurality of interconnect networks, and convert said second plurality of bit data generated in said interconnect network into one or more binary output data.
A processor comprising a plurality of logic circuits that execute a prescribed arithmetic operation, said logic circuits comprising:
- a plurality of decoders that convert one or more binary input data into a first plurality of bit data of a constant hamming weight regardless of a hamming weight of said input data;
- a plurality of interconnect networks that are connected to said plurality of decoders, substitutes a bit position of said first plurality of bit data for the purpose of said prescribed arithmetic operation and generate a second plurality of bit data, by receiving said first plurality of bit data converted by said connected decoder, and changing connection of a plurality of interconnect corresponding to each of received said first plurality of bit data;
- and
- a plurality of encoders that are connected to said plurality of interconnect networks, and convert said second plurality of bit data generated in said interconnect network into one or more binary output data.
Dependencies are inferred from the claim text.