Inductor Q factor enhancement apparatus has bias circuit that is coupled to negative resistance generator for providing bias signal

#1. Field of the Invention

#The present invention relates to a circuit, especially to a circuit capable of enhancing the Q factor of an inductor.

#2. Description of the Prior Art

#FIG. 1 is the circuit configuration of the present invention illustrating a negative resistance generator compensating for the parasitical resistors of the inductor.

#FIG. 2 is an equivalent circuit of the circuit shown in FIG. 1.

#FIG. 3 is an equivalent circuit of the circuit shown in FIG. 2.

#One method to enhance the Q factor of a chip inductor is reducing the power consumption of the chip inductor due to its parasitical resistor. The present invention adopts a negative resistance generator, which provides negative resistance, to compensate for the parasitical resistor of the chip inductor. Please refer to FIG. 1. FIG. 1 is the circuit configuration of the present invention illustrating a negative resistance generator 120 compensating for the parasitical resistors of inductors 112 and 114. The inductors 112 and 114 together with an operation circuit 116 construct an application circuit 110. The negative resistance generator 120 is coupled to the application circuit 110 to compensate for the parasitical resistors of the inductors 112 and 114. The negative resistance generator 120 comprises a pair of transistors 122 and 124, which couple to each other. In this embodiment, P-MOSFET's serve as exemplary devices for the transistors 122 and 124 for the sake of illustrating the configuration, but are not meant to be a limitation of the present invention. The gates of the transistors 122 and 124 are coupled to each other, and then further coupled to the drain of the transistor 122 through a capacitor 126 and to the drain of the transistor 124 through a capacitor 128. The capacitors 126 and 128 are AC coupled capacitors, utilized for separating DC components and AC components. Moreover, a voltage level Vc is coupled to the gates of the transistors 122 and 124 to bias the negative resistance generator 120. Under the ways of configuration and biasing described above, the negative resistance generator 120 can be regarded effectively as two resistors coupled in series. Thus, FIG. 1 is simplified to an equivalent circuit shown in FIG. 2. If the manufacturing parameters are the same for both transistors 122 and 124, then in this embodiment, the resistances of the equivalent resistors 212 and 214 shown in FIG. 2 are approximately −1/gm, where gm is the transconductance of the transistors 122 and 124.

#The connection among resistors 212, 214, and inductors 112, 114 can be further simplified to an equivalent circuit shown in FIG. 3. The resistor 310 is equivalent to the serial-coupled resistors 212 and 214, and the resistance R− of the resistor 310 is −2/gm. The inductor 320 is equivalent to the serial-coupled inductors 112 and 114, and is illustrated in FIG. 3 by a parasitical resistor 324 coupled in parallel with a real inductor 322. The resistance of the parasitical resistor 324 is RL, and the inductance of the inductor 322 is L. As shown in FIG. 3, it is well known to those skilled in the art that the Q factor of the inductor 320 is approximately equal to Rp/ωL, where, Rp is a resistance of the parallel-coupled resistors R− and RL, and ω is an angular frequency of inductors 112 and 114. Therefore, by properly biasing the negative resistance generator 120 and determining the resistance R− of the resistor 310, the parasitical resistor 324 of the inductor 320 can be compensated and therefore the Q factor of the inductor is enhanced.

#In the above-mentioned embodiment, the voltage level Vc, which is utilized to bias the negative resistance generator 120, is provided by a bias circuit. Please refer to FIG. 4. FIG. 4 shows the bias circuit 400 according to an embodiment of the present invention. The bias circuit 400 is a constant transconductance bias circuit. The bias circuit 400 comprises four transistors 410, 420, 430, 440 and a load unit 450. In this embodiment, two P-MOSFET's and two N-MOSFET's serve as exemplary devices for the transistors 410, 420, 430, and 440 for the sake of illustrating the configuration, but are not meant to be a limitation of the present invention. In FIG. 4, assuming that the sizes of the transistors 410, 420, 430, 440 are respectively (W/L)N, (W/L)N, K(W/L)P, (W/L)P (K is the ratio of the size of the transistor 430 to the size of the transistor 440), and the load unit 450 is a resistor with resistance Rs, then the output current IOUT of the bias circuit 400 is represented as