US 7,583,152 B2 · Phase-locked loop with self-correcting phase-to-digital transfer function

Abstract

A phase-locked loop includes a phase-to-digital converter portion as well as a novel correction portion. The phase-to-digital converter (PDC) portion outputs a stream of first phase error words. The novel correction portion receives the first phase error words and generates a stream of second phase error words that is supplied to a loop filter. The PDC portion has a phase-to-digital transfer function that exhibits certain imperfections. In a first example, the correction portion determines an average difference between pairs of first phase error words, and uses this average difference to normalize the first phase error words to correct for changes in PDC portion transfer function slope due to changes in delay element propagation delay. In a second example, the correction portion corrects for gain mismatches in PDC portion transfer function. In a third example, the correction portion corrects for offset mismatches in PDC portion transfer function.

Claims24

Dependent claims

A phase-locked loop (PLL) circuit comprising:

a digitally controlled oscillator (DCO) that outputs a first signal;
a loop divider that receives the first signal and outputs a second signal;
and
a phase-to-digital converter (PDC) that receives a reference signal and the second signal and generates a stream of second phase error words, wherein the PDC has an overall phase-to-digital transfer function, and wherein the PDC comprises:
a phase-to-digital converter portion that outputs a stream of first phase error words, the PDC portion having a first phase-to-digital transfer function;
and
a correction portion that receives the stream of first phase error words and generates the stream of second phase error words such that the overall phase-to-digital transfer function is different from the first phase-to-digital transfer function.

4 more elements

A method comprising:

(a) in a phase-to-digital (PDC) all-digital phase-locked loop (ADPLL) determining a first first phase error word dTi−1, wherein dTi−1 is determined when a loop divider of the PDC ADPLL is dividing by a divisor N;
(b) in the PDC ADPLL determining a second first phase error word dTi, wherein dTi is determined when the loop divider is dividing by a divisor N+1;
(c) using a difference between dTi and dTi−1 to determine a multiplier value;
(d) using the multiplier value to scale dTi−1 to generate a first second phase error word dTi−1_corr;
and
(e) using the multiplier value to scale dTi−1 to generate a second second phase error word dTi_corr.

3 more elements

Dependencies are inferred from the claim text.

Phase-locked loop with self-correcting phase-to-digital transfer function

Life of this patent

Phase-locked loop with self-correcting phase-to-digital transfer function

Life of this patent

Abstract

Claims24