VCO amplitude control

#The present invention relates generally to circuits and methods for controlling the amplitude of a signal generated by a voltage controlled oscillator (VCO), e.g., in a phase locked loop (PLL) with an LC-type VCO.

#Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.

#FIG. 1 is a diagram of a phase locked loop circuit in accordance with some embodiments.

#FIG. 2 is a flow diagram of a routine for controlling a VCO amplitude for the PLL of FIG. 1 in accordance with some embodiments.

#Inductor-capacitor voltage controlled oscillators (LCVCOs) may be used in a wide variety of applications including within phase locked loop (PLL) circuits to generate phase and/or frequency controlled clocks. They may be especially desired in high-frequency, low power applications because they can have less jitter due to favorable thermal noise immunity and power supply noise rejection. Unfortunately, it can be challenging to manufacture LCVCOs in commercial volumes due, among other things, to deviations in tank (LC) Q factor, which makes it difficult to achieve consistent signal amplitudes from product to product, as a result of differences in process and temperature. Small changes in the Q factor can cause significant amplitude deviations, and in some cases, oscillations may not even start at all. Accordingly, embodiments for controlling (or calibrating) oscillation amplitude are disclosed herein.

#FIG. 1 shows a PLL circuit using an LCVCO, in accordance with some embodiments. It generally comprises a phase-frequency detector (PFD) 102, a charge pump/loop filter (CP/LF) 104, an LC-type VCO 106 (with an automatic amplitude control circuit 108 and an automatic frequency control circuit 110), a divide-by-2 circuit 112, a buffer/level shifter (BLS) circuit 114, and a programmable divider 116, all coupled together as indicated. (Note that while single lines are used for convenience, the actual signals are not necessarily so limited. For example, they may comprise one or more lines, such as with differential signals or multi-bit digital signals.)

#The PFD 102 receives a reference clock signal (RefClk) and generates from it a phase and/or frequency aligned version of the reference clock at the output (OutClk) of the BLS circuit 114. It receives a fedback version (FbClk) of the generated clock (tapped from the output of the Divide-by-2 circuit in this case) and compares its phase and/or frequency with that of the reference clock to generate an error signal reflecting the phase/frequency difference. In this case, the error signal comprises an Up signal that asserts if the reference clock is ahead of the fedback clock and a Dn signal that asserts if the fedback clock is ahead of the reference clock. An assertion of the Up or Dn signal charges or discharges the charge pump/loop filter 104 to appropriately raise or lower a VCO control voltage (Vctl). This causes the LCVCO 106 to increase or decrease the phase/frequency of its generated clock in order to adjust for the difference between the reference and fedback clocks.