Charge pump circuit

A latch-type charge pump circuit including at least one first charge pump stage coupled to at least one second charge pump stage by an intermediate circuit node, the charge pump circuit comprising:

• a first pump capacitor coupled between a first enable terminal and a first inner circuit node;
• a second pump capacitor coupled between a second enable terminal and a second inner circuit node, the first and second enable terminals receiving phase signals that are complementary to one another;
• a third pump capacitor coupled between the second enable terminal and a third inner circuit node;
• a fourth pump capacitor coupled between the first enable terminal and a fourth inner circuit node;
• a first latch transistor coupled between the first inner circuit node and the intermediate circuit node;
• a second latch transistor coupled between the second inner circuit node and the intermediate circuit node;
• a third latch transistor coupled between the third inner circuit node and the intermediate circuit node;
• a fourth latch transistor coupled between the fourth inner circuit node and the intermediate circuit node;
• and
• a stabilization circuit including at least one stabilization stage coupled between the intermediate circuit node and the first and second enable terminals, the at least one stabilization stage being coupled to control terminals of the first, second, third, and fourth latch transistors for supplying these latch transistors with suitable control signals so as to ensure correct turn-on and turn-off during a charge sharing period of the charge pump circuit.