Delaying stage selecting circuit and method thereof

A delaying stage selecting circuit, for selecting a specific delaying stage from a plurality of delaying stages, the delaying stages used for outputting a plurality of delayed clock signals, the delaying stage selecting circuit comprising:

• a first register, coupled to the delaying stages, for sampling the delayed clock signals according to a clock signal to generate a plurality of sampled values;
• a plurality of first memory units, coupled to the first register, wherein the first memory units are utilized to memorize the sampled values, and each of the first memory unit outputs at least one of the sampled values according to a corresponding first selecting signal;
• a first selecting unit, coupled to the first memory units, for outputting the sampled values according to a second selecting signal;
• a determining module, coupled to the first selecting unit, for determining whether sampled values meet a specific relation to generate a determination result, and determining the particular delaying stage if the determination result is positive;
• and
• a counter, coupled to the determining module, for generating a counting value to control the delayed clock signal sampled by the first register.