High-speed flip-flop circuit

A flip-flop circuit, including a first power supply and a second power supply of a potential that is different from that of the first power supply, for capturing an input signal in sync with a clock, comprising:

• a first gate, including transistors connected in three stages between the first and second power supplies, that outputs a first signal corresponding with the input signal;
• a second gate, including transistors connected in three stages between the first and second power supplies, that generates a second signal of a first predetermined level in response to a first level of the clock and causes the second signal to be a level corresponding with the first signal in response to a second level of the clock;
• a third gate, including transistors connected in three stages between the first and second power supplies, that outputs a third signal corresponding with the second signal in response to the second level of the clock;
• a first inversion feedback circuit, provided between a terminal of the third signal and a terminal of the second signal, that is activated in response to the second level of the clock;
• and
• level fixing circuit that fixes the terminal of the first signal at a second predetermined level with a predetermined time delay after the clock changes to the second level.

A flip-flop circuit, including a first power supply and a second power supply of a potential that is different from that of the first power supply, that captures an input signal in sync with a clock, comprising:

• a first gate, including transistors connected in three stages between the first and second power supplies, that outputs a first signal corresponding with the input signal;
• a second gate, including transistors connected in three stages between the first and second power supplies, that generates a second signal of a first predetermined level in response to a first level of the clock and causes the second signal to be a level corresponding with the first signal in response to a second level of the clock;
• a combination circuit that is activated in response to the second level of the clock and outputs a third signal corresponding with the second signal;
• a first inversion feedback circuit, provided between a terminal of the third signal and a terminal of the second signal, that is activated in response to the second level of the clock;
• and
• level fixing circuit that fixes a terminal of the first signal at a second predetermined level with a predetermined time delay after the clock changes to the second level.