Receiver of digital signals having a variable hysteresis, in particular for audio digital application

A signal receiver inserted between a first and a second voltage reference and having a first and a second input terminal effective to receive differential signals and an output terminal effective to provide a converted signal, wherein the signal receiver comprises a conversion stage inserted between said first and second voltage references and connected between said first and second input terminals of said signal receiver and an input terminal of a hysteresis comparator, connected in turn to said output terminal of said signal receiver, said conversion stage performing a conversion from any input signal received on respective input terminals to an intermediate signal provided on an output terminal and suitable for reception by said hysteresis comparator;

• wherein said conversion stage performs an ALL-INPUT/single-ended conversion generating a trapezoidal signal;
• wherein said conversion stage is further connected to a bias terminal effective to receive a bias current;
• and
• wherein said conversion stage comprises:
• a first current mirror connected to said first voltage reference and to said input terminals, as well as to said bias terminal;
• a second current mirror connected to said second voltage reference and to said first input terminal, as well as to a circuit node;
• a third current mirror connected to said second voltage reference and to said second input terminal, as well as to said output terminal;
• and
• a fourth current mirror connected to said first voltage reference, to said circuit node, as well as to said output terminal.

A digital signal receiver, comprising:

• a converter having first and second input terminals adapted to receive respective input signals and a bias input adapted to receive a bias current, the converter operable to develop an intermediate signal on an intermediate output in response to the input signals and the intermediate signal having a hysteresis that is a function of the bias current;
• and
• a hysteresis comparator coupled to the intermediate output of the converter to receive the intermediate signal, and the hysteresis comparator operable to develop a trigger signal in response to the intermediate signal;
• and
• wherein the converter further comprises a resistor bridge and a plurality of MOS transistors, the resistor bridge operable to reduce voltages of the input signals to levels appropriate for the MOS transistors and operable to match an input impedance of the digital signal receiver at the input terminals to an input impedance of a source applying the input signals.

An integrated circuit, comprising:

• a digital signal receiver, including,
• a converter having first and second input terminals adapted to receive respective input signals and a bias input adapted to receive a bias current, the converter operable to develop an intermediate signal on an intermediate output in response to the input signals and the intermediate signal having a hysteresis that is a function of the bias current;
• and
• a hysteresis comparator coupled to the intermediate output of the converter to receive the intermediate signal, and the hysteresis comparator operable to develop a trigger signal in response to the intermediate signal;
• and
• wherein the converter further comprises a resistor bridge and a plurality of MOS transistors, the resistor bridge operable to reduce voltages of the input signals to levels appropriate for the MOS transistors and operable to match an input impedance of the digital signal receiver at the input terminals to an input impedance of a source applying the input signals.

An electronic system, comprising:

• an integrated circuit including a digital signal receiver, the digital signal receiver including,
• a converter having first and second input terminals adapted to receive respective input signals and a bias input adapted to receive a bias current, the converter operable to develop an intermediate signal on an intermediate output in response to the input signals and the intermediate signal having a hysteresis that is a function of the bias current;
• and
• a hysteresis comparator coupled to the intermediate output of the converter to receive the intermediate signal, and the hysteresis comparator operable to develop a trigger signal in response to the intermediate signal;
• and
• wherein the converter further comprises a resistor bridge and a plurality of MOS transistors, the resistor bridge operable to reduce voltages of the input signals to levels appropriate for the MOS transistors and operable to match an input impedance of the digital signal receiver at the input terminals to an input impedance of a source applying the input signals.

A signal receiver inserted between a first and a second voltage reference and having a first and a second input terminal effective to receive differential signals and an output terminal effective to provide a converted signal, the signal receiver comprising:

• a hysteresis comparator including an input terminal, the hysteresis comparator being connected to said output terminal of said signal receiver;
• a conversion stage inserted between said first and second voltage references and connected between said first and second input terminals of said signal receiver and the input terminal of the hysteresis comparator, connected in turn to said output terminal of said signal receiver, said conversion stage performing a conversion from any input signal received on respective input terminals to an intermediate signal provided on an output terminal and suitable for reception by said hysteresis comparator;
• wherein said conversion stage comprises:
• a first current mirror connected to said first voltage reference and to said input terminals, as well as to said bias terminal;
• a second current mirror connected to said second voltage reference and to said first input terminal, as well as to a circuit node;
• a third current mirror connected to said second voltage reference and to said second input terminal, as well as to said output terminal;
• and
• a fourth current mirror connected to said first voltage reference, to said circuit node, as well as to said output terminal;
• wherein the second and third current mirrors are coupled to the first and second input terminals, respectively, through a resistor bridge operable to reduce voltages of the input signals to appropriate for a plurality of MOS transistors and operable to match an input impedance of the digital signal receiver at the input terminals to an input impedance of a source applying the input signals.