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US 7,583,118 B2Granted
Delay locked loop circuit
AssigneeNEC Electronics Corporation
InventorsAtsushi Hasegawa, Atsushi Tangoda
Life of this patent
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Abstract
A delay locked loop (DLL) circuit includes a first DLL section configured to receive a reference clock signal, to delay the reference clock signal in response to a first control signal, and to output a phase delayed signal having a predetermined phase delay. A second DLL section delays the reference clock signal in response to a second control signal, and generates the second control signal based on the reference clock signal delayed in the second DLL section and the phase delayed signal. An input signal delay section delays an input signal in response to the second control signal.
Claims16
A delay locked loop (DLL) circuit, comprising:
- a first DLL section configured to receive a reference clock signal, to delay said reference clock signal in response to a first control signal, and to output a phase delayed signal having a predetermined phase delay;
- a second DLL section, coupled in series to the first DLL section with respect to the reference clock signal, configured to delay said reference clock signal in response to a second control signal, and to generate said second control signal based on said reference clock signal delayed in said second DLL section and said phase delayed signal;
- and
- an input signal delay section configured to delay an input signal in response to said second control signal,
- wherein said first DLL section comprises:
- a first delay section configured to delay said reference clock signal over a plurality of delay stages in response to said first control signal;
- and
- a first control circuit configured to generate said first control signal from the reference clock signal and said reference clock signal delayed over said plurality of delay stages,
- wherein said first delay section outputs the delayed reference clock signals from some of said plurality of delay stages, and
- wherein said first DLL section further comprises:
- a first fixed delay circuit having a first fixed delay amount and configured to generate said phase delayed signal from some delayed reference clock signals.
8 more elements
A delay locked loop (DLL) circuit, comprising:
- a first DLL section configured to receive a reference clock signal, to delay said reference clock signal in response to a first control signal, and to output a phase delayed signal having a predetermined phase delay;
- a second DLL section, coupled in series to the first DLL section with respect to the reference clock signal, configured to delay said reference clock signal in response to a second control signal, and to generate said second control signal based on said reference clock signal delayed in said second DLL section and said phase delayed signal;
- and
- an input signal delay section configured to delay an input signal in response to said second control signal,
- wherein said first DLL section comprises;
- a first delay section configured to delay said reference clock signal over a plurality of delay stages in response to said first control signal;
- and
- a first control circuit configured to generate said first control signal from the reference clock signal and said reference clock signal delayed over said plurality of delay stages,
- wherein said first delay section outputs the delayed reference clock signal from one of said plurality of delay stages as said phase delayed signal, and
- wherein said second DLL section comprises:
- a second delay section configured to delay said reference clock signal in response to said first and second control signals;
- a third fixed delay circuit having a third fixed delay amount which is predetermined and configured to delay said reference clock signal delayed by said second delay section by said third fixed delay amount;
- and
- a second control circuit configured to generate said second control signal from said reference clock signal delayed by said second delay section and said phase delayed signal.
11 more elements
A delay locked loop (DLL) circuit, comprising:
- a first DLL section configured to receive a reference clock signal, to delay said reference clock signal in response to a first control signal, and to output a phase delayed signal having a predetermined phase delay;
- a second DLL section, coupled in series to the first DLL section with respect to the reference clock signal, configured to delay said reference clock signal in response to a second control signal, and to generate said second control signal based on said reference clock signal delayed in said second DLL section and said phase delayed signal;
- and
- an input signal delay section configured to delay an input signal in response to said second control signal,
- wherein said second DLL section comprises a delay section configured to delay said reference clock signal in response to said first and second control signals.
2 more elements
A delay locked loop (DLL) circuit, comprising:
- a first DLL section configured to receive a reference clock signal, to delay said reference clock signal in response to a first control signal generated from said first DLL section, and to output a phase delayed signal;
- a second DLL section configured to delay said reference clock signal in response to a second control signal, and to generate said second control signal based on said reference clock signal delayed in said second DLL section and said phase delayed signal;
- and
- an input signal delay section configured to delay an input signal in response to said second control signal,
- wherein said second DLL section comprises a delay section configured to delay said reference clock signal in response to said first and second control signals.
2 more elements
Dependencies are inferred from the claim text.