Delay lock clock synthesizer and method thereof
AssigneeRealtek Semiconductor Corp.
InventorsChia-Liang Lin, Gerchih Chou
Life of this patent
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Abstract
A delay lock clock synthesizer comprises: an adjustable delay circuit for receiving an input clock and for generating an output clock having a phase offset controlled by a control signal; a phase detector for detecting a phase difference between the input clock and the output clock and for generating a phase error signal representing the phase difference; a summing circuit for summing the phase error signal and a phase offset signal into a modified phase error signal; and a filter for filtering the modified phase error signal to generate the control signal to control the adjustable delay circuit.
Claims17
An apparatus comprising:
- an adjustable delay circuit for receiving an input clock and for generating an output clock having a phase offset determined by a control signal;
- a phase detector for detecting a phase difference between the input clock and the output clock and for generating a phase error signal representing the phase difference;
- an encoder for receiving an input code and thereby converting the input code into a plurality of output codes;
- a plurality of converters for converting said output codes into a plurality of analog signals, respectively;
- a summing circuit for summing the phase error signal and the plurality of analog signals into a modified phase error signal;
- and
- a filter for filtering the modified phase error signal to generate the control signal.
A method of generating an output clock, the method comprising:
- receiving an input clock;
- generating the output clock by delaying the input clock by an amount of delay controlled by a control signal;
- detecting a phase difference between the input clock and the output clock to generate a phase error signal;
- converting an input code into a plurality of output codes;
- performing a plurality of digital-to-analog conversions to convert said output codes into a plurality of analog signals, respectively;
- summing the phase error signal and the plurality of analog signals into a modified phase error signal;
- and
- filtering the modified phase error signal to generate the control signal.
Dependencies are inferred from the claim text.