US 7,583,115 B2 · Delay line off-state control with power reduction

Abstract

A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state.

Drawings

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Drawings

Claims41

Dependent claims

A device comprising:

a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal received by said delay lock loop, said delay lock loop comprising:
a register configured to provide a signal to control a delay operation;
at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state, the at least one delay circuit having at least one delay element operatively coupled to the register and comprising:
a first NAND gate to receive an entry point delay signal;
a second NAND gate operatively coupled to said first NAND gate, said second NAND gate configured to receive a first input from said first NAND gate and a second input from said register, said second NAND gate configured to provide a delayed output signal;
and
an AOI gate coupled to a bit associated with said register and to said first NAND gate, said AOI gate configured to receive an input signal and provide an output to said first NAND gate to provide a delay upon said input signal to cause said second NAND gate to generate said output signal.

4 more elements

A delay lock loop for providing an output signal based upon a phase difference between a reference signal and a feedback signal, comprising:

a register configured to provide a signal to control a delay operation;
a delay unit operatively coupled to the register and configured to delay at least one of the reference signal and the output signal, the delay unit comprising:
a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state associated with said delay unit;
at least one delay element comprising:
a first NAND gate to receive an entry point delay signal;
a second NAND gate operatively coupled to said first NAND gate, said second NAND gate configured to receive a first input from said first NAND gate and a second input from said register, said second NAND gate configured to provide a delayed output signal;
and
an AOI gate coupled to a bit associated with said register and to said first NAND gate, said AOI gate configured to receive an input signal and provide an output to said first NAND gate to provide a delay upon said input signal to cause said second NAND gate to generate said output signal;
a feedback delay unit operatively coupled to said delay unit, said feedback delay unit configured to provide a delay upon said output signal to generate said feedback signal;
and
a phase detector operatively coupled to said feedback unit, said phase detector configured to recognize a phase difference between said reference signal and said feedback signal.

8 more elements

A system board comprising:

a first device comprising:
a memory location configured to store data;
and
a delay lock loop configured to provide an output signal based upon a phase difference between a reference signal and a feedback signal received by said delay lock loop, said delay lock loop comprising:
a register configured to provide a signal to control a delay operation;
at least one delay circuit comprising a plurality of logic gates logic gates configured to provide for substantially uniform degradation each NAND in a NAND-NAND pair, the delay circuit comprising at least one delay element operatively coupled to the register, the delay element comprising:
a first NAND gate to receive an entry point delay signal;
a second NAND gate operatively coupled to said first NAND gate, said second NAND gate configured to receive a first input from said first NAND gate and a second input from said register, said second NAND gate configured to provide a delayed output signal;
and
an AOI gate coupled to a bit associated with said register and to said first NAND gate, said AOI gate configured to receive an input signal and provide an output to said first NAND gate to provide a delay upon said input signal to cause said second NAND gate to generate said output signal;
and
a second device operatively coupled to said first device, said second device configured to access data from said first device based upon an operation performed by said delay lock loop.

9 more elements

Dependencies are inferred from the claim text.

Description7,043 words

Summary1,737 words

#1. Field of the Invention

#This invention relates generally to a semiconductor memory device, and, more specifically, to controlling a delay line for achieving power reduction.

#2. Description of the Related Art

Brief description of the drawings8 figures

#The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:

#FIG. 1 is a simplified circuit diagram of a prior art delay line unit cell utilized in a prior art delay lock loop system;

#FIG. 2 is a block diagram of a system including a device that is capable of accessing digital data, in accordance with one embodiment of the present invention;

Detailed description5,077 words

#While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

#Illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

#Synchronization between multiple digital signals in a digital system is important for accurate exchange of digital data. Often, delay lock loops are employed to synchronize digital signals. For example, a NAND gate that has a static high state applied to one input may degrade differently than a NAND gate with a static low applied to the same corresponding input, causing the high-to-low or low-to-high times to be unequal in relation to the corresponding propagation time periods of other NAND gates in the delay element 520. This may cause duty cycle distortion through the delay element, i.e., pair of NANDs. For example, the duty cycle may be calculated as a ratio of the time period where a signal is high, versus the clock period. For example, for memory devices such as double data rate DRAM (DDR-DRAM, DDR I device, DDR II device), if there is a two nanosecond cycle time, the “high” time period should be substantially equal to one nanosecond. Similarly, the “low” time period should be substantially equal to one nanosecond. For DDR-DRAM, these “low” and “high” time periods generally directly translate to input and/or output data windows since data transitions may be made on the high edge and the falling edge of a clock signal. Duty cycle distortion may occur when some time period is taken away from either the high time period or from the low time period. For example, for the two nanosecond cycle time described above, if the high time period is less than one nanosecond, or if the low time period is less than one nanosecond, a duty cycle distortion problem may occur. In other words, the window for proper data transitions may become smaller and data errors may occur.

Facts

Application

10/927,248Filed 26 Aug 2004

Published

US 2006/0044029 A12 Mar 2006

Granted

1 Sep 2009

Term ended

31 Mar 2025

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 217 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification8 codes

H03L 7/0802
Details of the phase-locked loop: the loop being adapted for reducing power consumption
G11C 7/22
Arrangements for writing information into, or reading information out from, a digital store: read-write [R-W] timing or clocking circuits;…
G11C 7/222
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…
H03L 7/0814
And where no voltage or current controlled oscillator is used: the phase shifting device being digitally controlled

Timeline

26 Aug 2004Application filedUS 10/927,248
26 Aug 2004Assigned to Micron Technology, Inc.assignment of assignor's interest
2 Mar 2006PublishedUS 2006/0044029 A1
1 Sep 2009GrantedUS 7,583,115 B2
12 May 2016Assigned to U.S. Bank National Association, AS Collateral Agentsecurity interest
2 Jun 2016Assigned to Morgan Stanley Senior Funding, Inc., AS Collateral Agentpatent security agreement
8 Jun 2017Assigned to U.S. Bank National Association, AS Collateral Agentcorrective assignment to correct the replace erroneously filed patent #7358718 with the correct patent #7358178 previously recorded on reel 038669 frame 0001. assignor(s) hereby confirms the security interest.
13 Jul 2018Assigned to Jpmorgan Chase Bank, N.A., AS Collateral Agentsecurity interest
23 Aug 2018Assigned to Micron Technology, Inc.release of security interest
9 Oct 2019Assigned to Micron Technology, Inc.release of security interest
12 Nov 2019Assigned to Micron Technology, Inc., Micron Semiconductor Products, Inc.release of security interest
31 Mar 2025Term endedEstimated, includes 217 days of adjustment

Delay line off-state control with power reduction

Life of this patent

Delay line off-state control with power reduction

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims41

Description7,043 words

Drawings

Classification8 codes

Life of this patent

Description7,043 words