Method for driving a transistor half-bridge
AssigneeInfineon Technologies AG
InventorMaurizio Galvano
Life of this patent
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Abstract
A method drives a transistor half-bridge. The method includes measuring a delay time between an edge of an input signal and an corresponding edge of a phase signal, and saving the delay time as a saved delay time value. The phase signal is the output of the transistor half-bridge. In the method, the following steps are repeated until the saved delay time value differs from the delay time by more than a given threshold: decrementing the delay-value of a programmable delay circuit and the saved delay time value by a given decrement, the programmable delay circuit coupled to a control terminal of a first transistor of the half-bridge, and measuring the delay time between an edge of the input signal and an corresponding edge of the phase signal.
Claims10
A method for driving a transistor half-bridge comprising
- (A) measuring a delay time between an edge of an input signal and an corresponding edge of a phase signal, the phase signal comprising the output signal of the transistor half-bridge,
- (B) saving said delay time to generate a saved delay time value,
- (C) decrementing said delay value of a programmable delay circuit and said saved delay time value by a given decrement, the programmable delay disposed between the a node containing the input signal and a control terminal of a first transistor of the transistor half-bridge,
- (D) measuring said delay time between an edge of said input signal and an corresponding edge of said phase signal,
- (E) repeating steps C to E until said saved delay time value differs from said delay time by more than a given threshold.
A method for driving a transistor half-bridge, comprising:
- (A) measuring a delay time between an edge of an input signal and a corresponding edge of a phase signal, the phase signal comprising the output signal of the transistor half-bridge,
- (B) saving said delay time in order to generate a saved delay time value,
- (C) decrementing said delay value of a programmable delay circuit and said saved delay time value by a given decrement, the programmable delay disposed between the a node containing the input signal and a control terminal of a first transistor of the transistor half-bridge,
- (D) providing a time-shifted signal which is a time-shifted version of said input-signal shifted by said saved delay time value,
- (E) measuring the time difference between an edge in said time-shifted signal and said phase signal,
- (F) repeating steps C to F until said time-difference exceeds a certain threshold.
A circuit arrangement comprising:
- a half bridge comprising
- a first transistor having a first load terminal, a second load-terminal, and a control terminal receiving a first control-signal,
- a second transistor having a first load terminal, a second load terminal, and a control terminal receiving a second control signal, wherein
- said second load terminal of said first transistor and said first load terminal of said second transistor both are connected to a phase terminal providing a phase signal;
- and
- a control circuit comprising
- a feedback terminal connected to said phase terminal,
- a driver circuit adapted for providing said first and second control signals and comprising a programmable delay circuit operably connected to said control terminal of said first transistor,
- a processing circuit configured to
- measure a delay time between an edge of said input signal and an corresponding edge of said phase signal,
- save said delay time and decrementing a saved delay time and a delay value of said programmable delay circuit, and
- compare said delay time with a saved delay time value.
Dependencies are inferred from the claim text.