Clock circuitry

A method comprising:

• supplying a first clock signal having a first faster frequency to a first circuit portion;
• supplying a second clock signal having a second slower frequency to a second circuit portion;
• generating a first control signal at a predetermined time in each cycle of the first clock signal prior to a predetermined edge of the first clock signal;
• generating a second control signal at a predetermined time in each cycle of the second clock signal prior to a predetermined edge of the second clock signal;
• varying the relative frequency of the first and second clock signals on the condition of detecting a coincidence of the first and second control signals;
• generating pulses based on the first and second clock signals to indicate when to transfer data between the first circuit portion and the second circuit portion, such that there is at least one cycle of the first clock signal between said pulses, and such that there is only one pulse per cycle of the second clock signal;
• producing a gated clock signal by gating the first clock signal so as to pass it when said pulses are asserted;
• and
• transferring data between the first circuit portion and the second circuit portion, the transfer being clocked by the gated clock signal.

A circuit comprising:

• clock circuitry comprising clock generating means arranged to supply a first clock signal having a first faster frequency to a first circuit portion and a second clock signal having a second slower frequency to a second circuit portion, the clock generating means being operable to select between a plurality of predetermined ratios between the first and second clock frequencies;
• synchronisation logic for generating pulses based on the first and second clock signals, each pulse indicating when to transfer data between the first circuit portion and the second circuit portion;
• gating means arranged to produce a gated clock signal by gating the first clock signal, the gating means being open when said pulses are asserted;
• and
• transfer means arranged to transfer data between the first circuit portion and the second circuit portion when clocked by the gated clock signal;
• wherein the synchronisation logic comprises a chain of at least two flip-flops arranged to shift through the second clock signal when clocked by the first clock signal, and combinational logic arranged to generate said pulses in dependence on a combination of outputs from each of said flip-flops;
• and
• the combinational logic is arranged to receive a ratio indication signal indicative of the ratio between the first and second frequencies, and to generate said pulses using said ratio indication signal such that regardless of the selected ratio:
• there is at least one cycle of the first clock signal between said pulses, and there is only one of said pulses per cycle of the second clock signal.

A method comprising:

• supplying a first clock signal having a first faster frequency to a first circuit portion;
• supplying a second clock signal having a second slower frequency to a 20 second circuit portion;
• selecting the relative frequency between the first and second clock signals from a plurality of predetermined ratios;
• shifting the second clock signal through a chain of at least two flip-flops, the shifting being clocked by the first clock signal;
• receiving a ratio indication signal indicative of the ratio between the first and second frequencies;
• generating pulses which indicate when to transfer data between the first circuit portion and the second circuit portion, by using a combination of outputs from each of said flip-flops and said ratio indication signal such that, regardless of the selected ratio, there is at least one cycle of the first clock signal between said pulses, and there is only one pulse per cycle of the second clock signal;
• producing a gated clock signal by gating the first clock signal so as to pass it when the pulses are asserted;
• and
• transferring data between the first circuit portion and the second circuit portion, the transfer being clocked by gated clock signal.