Semiconductor device with multi-trench separation region and method for producing the same
AssigneeMitsubishi Denki Kabuhsiki Kaisha
InventorKazuhiro Shimizu
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Abstract
A semiconductor device is configured that a high-withstand voltage semiconductor device (101) and logic circuits (201 and 301) are integrated on a single chip and that a high-withstand voltage high-potential island (402) including the high-potential-side logic circuit (301) is separated using multiple partition walls enclosing therearound. The semiconductor device is provided with a multi-trench separation region (405) having a level shift wire region (404) that is used to connect the high-potential-side logic circuit to the high-potential-side electrode of the high-withstand voltage semiconductor device.
Claims17
A semiconductor device in which a high withstand voltage semiconductor device and logic circuits are integrated on a single chip, comprising:
- said high-withstand voltage semiconductor device having an oxide film and an epitaxial layer on a support substrate,
- a high-potential-side logic circuit connected to the high-potential-side electrode of said high-withstand voltage semiconductor device,
- a low-potential-side logic circuit that outputs control signals for controlling the driving of said high-withstand voltage semiconductor device, and
- a multi-trench separation region that separates a high-potential island including said high-potential-side logic circuit, that is formed of multiply overlaid trench separation regions biased by using capacitance couplings and that has a level shift region for connecting said high-potential-side logic circuit to the high-potential-side electrode of said high-withstand voltage semiconductor device and wherein
- a part of said multiply overlaid trench separation regions is arranged to overlap with a part of said high-withstand voltage semiconductor device, and
- said level shift region is biased by the capacitance coupling to have high-potential in said multiply overlaid trench separation regions, and is arranged in an area overlapping with the part of said high-potential-side logic circuit, so as to connect said high-potential-side logic circuit to the high-potential-side electrode of said high-withstand voltage semiconductor device.
A method for producing a semiconductor device in which a high-withstand voltage semiconductor device and logic circuits are integrated on a single chip, said semiconductor device comprising:
- the high-withstand voltage semiconductor device having an oxide film and an epitaxial layer on a support substrate
- a high-potential-side logic circuit connected to the high-potential-side electrode of said high-withstand voltage semiconductor device,
- a low-potential-side logic circuit that outputs control signals for controlling the driving of said high-withstand voltage semiconductor device, and
- a multi-trench separation region that separates a high-potential island including said high-potential-side logic circuit, that is formed of multiply overlaid trench separation regions biased by using capacitance couplings and that has a level shift wire region for connecting said high-potential-side logic circuit to the high-potential-side electrode of said high-withstand voltage semiconductor device, and wherein
- a part of said multiply overlaid trench separation regions is arranged to overlap with a part of said high-withstand voltage semiconductor device, and
- said level shift region is biased by the capacitance coupling to have high-potential in said multiply overlaid trench separation regions, and is arranged in a region, which overlaps with the part of said high-potential-side logic circuit, so as to connect said high-potential-side logic circuit to the high-potential-side electrode of said high-withstand voltage semiconductor device,
- wherein said method includes forming said level shift wire region by carrying out:
- a step of forming trenches in said epitaxial layer by carrying out anisotropic etching,
- a step of oxidizing the interiors of said trenches and burying polysilicon in said trenches,
- a step of etching said polysilicon while leaving said polysilicon inside said trenches, oxidizing the surface, accumulating a nitride film, and carrying out patterning,
- a step of eliminating said nitride film by carrying out selective oxidation and accumulating an interlayer oxide film, and
- a step of partially etching said interlayer oxide film and forming electrodes by carrying out metal accumulation.
Dependencies are inferred from the claim text.