US 7,582,927 B2 · Flash EEPROM cell and method of fabricating the same

Abstract

A semiconductor device including a memory cell having a memory transistor and select gate transistor and a peripheral transistor is disclosed. The memory transistor has a stacked gate structure formed by sequentially stacking a gate insulating film, first gate electrode, inter-poly insulating film, and second gate electrode on a semiconductor substrate. The select gate transistor has a stacked gate structure identical to the memory transistor, and selects the memory transistor. The peripheral transistor forms a peripheral circuit of the memory cell, and has a gate electrode having a single-layer structure. A through hole reaching the first gate electrode is formed in the second gate electrode and inter-poly insulating film positioned on an element isolation film of the select gate transistor. A contact plug buried in this through hole electrically connects the second gate electrode and first gate electrode.

Claims13

Dependent claims

A semiconductor device comprising:

a memory transistor having a stacked gate structure formed by sequentially stacking a gate insulating film, a first gate electrode, a inter-poly insulating film, and a second gate electrode on a semiconductor substrate;
a select gate transistor which has a stacked gate structure identical to the memory transistor, and selects the memory transistor;
a first contact plug buried in a through hole and electrically connecting the second gate electrode and the first gate electrode, the through hole is formed in the second gate electrode and the inter-poly insulating film positioned on an element isolation film in the select gate transistor, and reaching the first gate electrode;
and
a peripheral transistor which forms a peripheral circuit of a memory cell including the memory transistor and the select gate transistor, and includes a gate electrode with a single-layer structure.

2 more elements

A semiconductor device comprising:

a memory transistor having a stacked gate structure formed by sequentially stacking a gate insulating film, a first gate electrode, a inter-poly insulating film, and a second gate electrode on a semiconductor substrate;
a select gate transistor which has a stacked gate structure identical to the memory transistor, and selects the memory transistor;
a first silicide layer formed on an upper surface of the second gate electrode, on sidewalls of a through hole, and on the first gate electrode positioned in a bottom portion of the through hole, and electrically connecting the second gate electrode and the first gate electrode, the through hole is formed in the second gate electrode and the inter-poly insulating film positioned on an element isolation film in the select gate transistor, and reaching the first gate electrode;
and
a peripheral transistor which forms a peripheral circuit of a memory cell comprising the memory transistor and the select gate transistor, and includes a gate electrode with a single-layer structure.

2 more elements

Dependencies are inferred from the claim text.

Flash EEPROM cell and method of fabricating the same

Life of this patent

Flash EEPROM cell and method of fabricating the same

Life of this patent

Abstract

Claims13