Electrically rewritable non-volatile memory element and method of manufacturing the same
AssigneeElpida Memory, Inc.
InventorIsamu Asano
Life of this patent
Estimating the term…
Abstract
A non-volatile memory element includes a lower electrode, an upper electrode, a recording layer arranged between the lower electrode and the upper electrode and containing a phase change material, and a bit line directly arranged on the upper electrode. The bit line is formed to be offset to the recording layer. With this arrangement, a contact area between the recording layer and the upper electrode and a contact area between the upper electrode and the bit line can be reduced without providing an interlayer insulation film between the upper electrode and the bit line. Thus, heat radiation to the bit line can be suppressed while the upper electrode and the bit line are connected without using a through-hole.
Claims13
A non-volatile memory element, comprising:
- a lower electrode;
- an upper electrode;
- a recording layer containing a phase change material arranged between the lower electrode and the upper electrode;
- and
- a bit line substantially directly arranged on the upper electrode, wherein
- the bit line is offset to the recording layer.
A non-volatile memory element, comprising:
- an interlayer insulation film having a through-hole;
- a recording layer containing a phase change material formed in the through-hole;
- a lower electrode connected to a bottom surface of the recording layer;
- an upper electrode connected to a top surface of the recording layer;
- and
- a bit line arranged on the interlayer insulation film and connected to the upper electrode, wherein
- at least one of the upper electrode and the bit line is formed so that the edge traverses the through-hole.
A non-volatile memory element, comprising:
- a recording layer containing a phase change material, and having a plug shape;
- a lower electrode in contact with a part of a bottom surface of the recording layer;
- and
- a laminate wiring layer of an upper electrode and a bit line being on the upper electrode,
- wherein the laminate wiring layer is in contact with a part of a top surface of the recording layer, and an edge of the laminate wiring later intersects with the top surface of the recording layer.
Dependencies are inferred from the claim text.