Electronic device with an array of processing units
AssigneeKoninklijke Philips Electronics N.V.
InventorsMichael Overdick, Walter Ruetten
Life of this patent
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Abstract
Electronics devices like X-ray detectors with an array of pixels are combined (binned) into binning blocks of m×n pixels. Available read-out lines of the device are all connected to different binning blocks, such that up to m binning blocks are addressed simultaneously in the vertical direction when m×n binning is used. In this case, the output signals from the m vertically arranged blocks are distributed over the m read-out columns present in the m×n locks. Row address lines together with diagonal address lines and a simple activation logic provide the required versatile addressing of the pixels.
Claims16
An electronic device, comprising:
- an array of processing units, wherein each processing unit has an external coupling node and an internal coupling node;
- a binning circuit for selectively connecting the internal coupling nodes of several processing units each, wherein a set of coupled processing units constitutes a binning block;
- an addressing circuit for selectively addressing selected processing units;
- a number of signal lines, wherein the external coupling nodes of the processing units can selectively be connected to one of said signal lines under control of the addressing circuit in such a way that each of the signal lines is coupled to a different binning block;
- wherein the addressing circuit comprises row address lines that are connected to a selection logic in each processing unit of a corresponding row, and diagonal address lines that are connected to said selection logic in each processing unit, and wherein the selection logic is adapted to cause a connection of the external coupling node of the processing unit to a corresponding signal line if and only if both a corresponding row address line and a corresponding diagonal address line are activated.
An electronic device, comprising:
- an array of processing units, wherein each processing unit has an external coupling node and an internal coupling node;
- a binning circuit for selectively connecting the internal coupling nodes of several processing units each, wherein a set of coupled processing units constitutes a binning block;
- an addressing circuit for selectively addressing selected processing units;
- a number of signal lines, wherein the external coupling nodes of the processing units can selectively be connected to one of said signal lines under control of the addressing circuit in such a way that each of the signal lines is coupled to a different binning block;
- wherein the addressing circuit comprises row address lines that are connected to a selection logic in each processing unit of a corresponding row, and diagonal address lines that are connected to said selection logic in each processing unit;
- and
- wherein each diagonal address line is connected to one of the binning control lines that run along columns of the array.
A method for accessing binning blocks with several processing units in an electronic device with an array of processing units and a set of signal lines, the method comprising the acts of:
- connecting a diagonal address line and a row address line to a selection logic of a processing unit, wherein the selection logic is adapted to cause a connection of an external coupling node of the processing unit to a signal line if and only if both the row address line and the diagonal address line are activated;
- and
- addressing the processing units such that each of the signal lines accesses a different binning block.
An electronic device, comprising:
- processing units each having an external coupling node and an internal coupling node;
- a binning circuit for selectively connecting the internal coupling node of a plurality of the processing units to form a binning block;
- an addressing circuit for selectively addressing selected processing units, wherein the addressing circuit comprises a row address line and a diagonal address line;
- and
- a selection logic that receives the row address line and the diagonal address line, and wherein the selection logic is adapted to cause a connection of the external coupling node of the processing unit to a signal line if and only if both the row address line and the diagonal address line are activated.
Dependencies are inferred from the claim text.