US 7,582,567 B1 · Method for forming CMOS device with self-aligned contacts and region formed using salicide process

Abstract

A method for forming CMOS devices on a semiconductor substrate is disclosed in which gate structures are formed within both the core region and the non-core region of the semiconductor substrate. The gate structures include a gate dielectric layer and a gate film stack that includes a conductive layer and an overlying hard mask. The hard mask is then removed from the gate structures in the non-core region. A salicide process is then performed so as to form a silicide layer in the non-core region. A barrier layer is formed that extends over the core region and a pre-metal dielectric film is formed that extends over the barrier layer. A selective etch process is performed so as to form self-aligned contact openings that extend through the pre-metal dielectric film and through the barrier layer in the core region. These openings are then filled with conductive material to form self-aligned contacts in the core region. This produces a CMOS device in the core region that has high device density and includes high-speed CMOS devices the non-core region.

Claims20

Dependent claims

A method for forming complimentary metal oxide semiconductor (CMOS) devices on a semiconductor substrate comprising:

forming gate structures within a first region and within a second region of the semiconductor substrate, the gate structures including a conductive layer and a hard mask that overlies the conductive layer;
forming a first dielectric layer that extends over the gate structures;
and
performing a first etch process so as to remove the hard mask from the gate structures in the second region of the semiconductor substrate and expose the conductive layer, the first etch process removing portions of the first dielectric layer and exposing some of the top surface of the semiconductor substrate in the second region;
performing a salicide process so as to form a plurality of silicide segments in the second region of the semiconductor substrate;
forming self-aligned contacts within the first region of the semiconductor substrate;
and
forming contacts within the second region of the semiconductor substrate that are not self-aligned contacts.

5 more elements

A method for forming complimentary metal oxide semiconductor (CMOS) devices on a semiconductor substrate comprising:

forming gate structures within a first region and within a second region of the semiconductor substrate, the gate structures including a conductive layer that overlies the first dielectric layer and a hard mask that overlies the conductive layer;
forming a first dielectric layer on the semiconductor substrate such that the first dielectric layer overlies the gate structures;
and
forming a second dielectric layer that extends over the first dielectric layer;
performing a first etch process so as to remove the hard mask from the gate structures in the second region of the semiconductor substrate and expose the conductive layer, the first etch process removing portions of the second dielectric layer and portions of the first dielectric layer so as to expose some of the top surface of the semiconductor substrate in the second region;
performing a salicide process so as to form a plurality of silicide segments in the second region of the semiconductor substrate;
depositing additional dielectric material, the remaining portion of the second dielectric layer and the additional dielectric material forming a pre-metal dielectric film that immediately overlies the first dielectric layer in the first region;
and
forming self-aligned contacts within the first region of the semiconductor substrate.

6 more elements

A method for forming complimentary metal oxide semiconductor (CMOS) devices on a semiconductor substrate comprising:

forming gate structures within a first region and within a second region of the semiconductor substrate, the gate structures including a conductive layer and a hard mask that overlies the conductive layer;
forming a first dielectric layer on the semiconductor substrate such that the first dielectric layer overlies the gate structures;
forming a second dielectric layer that extends over the first dielectric layer;
performing a first etch process so as to remove the hard mask from the gate structures in the second region of the semiconductor substrate and expose the conductive layer, the first etch process removing portions of the second dielectric layer and portions of the first dielectric layer so as to expose some of the top surface of the semiconductor substrate in the second region;
performing a salicide process so as to form a plurality of silicide segments in the second region of the semiconductor substrate;
and
forming self-aligned contacts within the first region of the semiconductor substrate.

4 more elements

Dependencies are inferred from the claim text.

Method for forming CMOS device with self-aligned contacts and region formed using salicide process

Life of this patent

Method for forming CMOS device with self-aligned contacts and region formed using salicide process

Life of this patent

Abstract

Claims20