Method of fabricating complementary metal-oxide-semiconductor transistor and metal-oxide-semiconductor transistor

A method of fabricating a complementary metal-oxide-semiconductor (CMOS) transistor, comprising:

• providing a substrate having an isolation structure already formed thereon, wherein the isolation structure defines a first active region and a second active region;
• forming a first gate structure and a second gate structure on the substrate in the first and the second active regions respectively, wherein the first gate structure has a greater dimension than the second gate structure;
• forming first lightly doped drain regions in the substrate on two sides of the first gate structure in the first active region;
• after forming the first lightly doped drain regions, performing a first lightly doped drain annealing process;
• after performing the first lightly doped drain annealing process, forming second lightly doped drain regions, third lightly doped drain regions and fourth lightly doped drain regions in the substrate on two sides of the second gate structure in the first active region, on two sides of the first gate structure in the second active region and on two sides of the second gate structure in the second active region, respectively;
• forming first spacers on the sidewalls of the first and the second gate structures in the first active region and simultaneously forming second spacers on the sidewalls of the first and the second gate structures in the second active region;
• forming first source/drain regions in the substrate on two sides of the first spacers and forming second source/drain regions in the substrate on two sides of the second spacers;
• and
• performing a source/drain annealing process.

A method of fabricating a complementary metal-oxide-semiconductor (CMOS) transistor, comprising:

• providing a substrate having an isolation structure already formed thereon, wherein the isolation structure defines a first active region and a second active region;
• forming a first gate structure and a second gate structure on the substrate in the first and the second active regions respectively, wherein the first gate structure has a dimension greater than the second gate structure;
• forming first lightly doped drain regions in the substrate on two sides of the first gate structure in the first active region and forming second lightly doped drain regions in the substrate on two sides of the first gate structure in the second active region;
• after forming the first and the second lightly doped drain regions, performing a lightly doped drain annealing process;
• after performing the lightly doped drain annealing process, forming third lightly doped drain regions in the substrate on two sides of the second gate structure in the first active region and forming fourth lightly doped drain regions in the substrate on two sides of the second gate structure in the second active region;
• forming first spacers on the sidewalls of the first and the second gate structures in the first active region and simultaneously forming second spacers on the sidewalls of the first and the second gate structures in the second active regions;
• forming first source/drain regions in the substrate on two sides of the first spacers and forming second source/drain regions in the substrate on two sides of the second spacers;
• and
• performing a source/drain annealing process.