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US 7,582,494 B2Granted
Device structures for reducing device mismatch due to shallow trench isolation induced oxides stresses
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShine Chien Chung, David Lu
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Abstract
A circuit and method are disclosed for reducing device mismatch due to trench isolation related stress. One or more extended active regions are formed on the substrate, wherein the active regions being extended from one or more ends thereof, and one or more operational devices are placed on one or more active regions, wherein the extended active region has at least a length twice as much as a distance between gates of two neighboring operational devices.
Claims8
A method for reducing device performance mismatch due to stress incurred by trench isolation, the method comprising:
- providing a substrate;
- forming one or more extended active regions on the substrate, wherein the extended active regions being extended from one or more ends thereof;
- and
- placing one or more operational devices on one or more active regions,
- wherein the extended active region has at least a length twice as much as a distance between gates of two neighboring operational devices.
2 more elements
Dependencies are inferred from the claim text.