IC containing matrices of plural type operation units with configurable routing wiring group and plural delay operation units bridging two wiring groups

A method of designing an integrated circuit device that includes a data processing block in which a first matrix and a second matrix are included, the first matrix and the second matrix respectively including a plurality of types of operation units and a wiring group, a configuration of data flow with the plurality of types of operation units being changeable by changing a route of the wiring group, one of the plurality of types of operation units is a delay type operation unit that includes a data path suited to processing for delaying a transfer time of data, the wiring group of the first matrix and the wiring group of the second matrix being separated, a plurality of the delay type operation units being arranged along a boundary of the of the first matrix and the second matrix for connecting the wiring group of the first matrix and the wiring group of the second matrix via data paths included in the plurality of the delay type operation units,

• the method comprising the steps of:
• generating an execution configuration of a first flow by using place and route process with the plurality of types of operation units and the least one of the plurality of the delay type operation units that connect the wiring group of the first matrix and the wiring group of the second matrix;
• and
• generating an execution program that includes a process using the first data flow, for the integrated circuit device, the execution program including an instruction that indicates the execution configuration of the first data flow.