Redundancy circuit
AssigneeHynix Semiconductor Inc.
InventorsJae Hyuk Im, Yong Ju Chon
Life of this patent
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Abstract
A redundancy circuit can include a first fuse set that is configured to receive an address signal and an initializing signal activated when power is up, and to output a first redundancy signal, the first redundancy signal being used to repair a defective cell by using a laser beam radiating method, a second fuse set that is configured to receive the initializing signal, a specific address signal, a test mode signal that is activated when a defective cell exists, and the address signal, and to output a second redundancy signal, the second redundancy signal being used to repair the defective cell by using an electrical fusing method, a first memory cell array that is controlled by the first redundancy signal, and a second memory cell array that is controlled by the second redundancy signal.
Claims25
A redundancy circuit, comprising:
- a first fuse set that is configured to receive an address signal and an initializing signal activated when power is up, and to output a first redundancy signal, the first redundancy signal being used to repair a first defective memory cell by using a laser beam radiating method;
- a second fuse set that is configured to receive the initializing signal, a specific address signal, a test mode signal that is activated when a second defective memory cell is existent, and the address signal, and to output a second redundancy signal, the second redundancy signal being used to repair the second defective memory cell by using an electrical fusing method;
- a first memory cell array that is controlled by the first redundancy signal;
- and
- a second memory cell array that is controlled by the second redundancy signal.
A redundancy circuits comprising:
- a first fuse set circuit that includes a plurality of first fuse sets which is configured to receive an address signal and an initializing signal activated when power is up and to output a plurality of first redundancy signals;
- a second fuse set circuit that includes a plurality of second fuse sets which is configured to receive the initializing signal, a specific address signal, a test mode signal that is activated when a second defective memory cell is existent, and the address signal and to output a plurality of second redundancy signals;
- a first memory cell array that is controlled by the first redundancy signals;
- and
- a second memory cell array that is controlled by the second redundancy signals,
- wherein the first fuse set is configured to output the first redundancy signal for driving a redundancy word line of the first memory cell array in response to a first defective memory cell occurring in a wafer state, and
- wherein the second fuse set is configured to output the second redundancy signal for driving a redundancy word line of the second memory cell array in response to the second defective memory cell occurring in the wafer state and a package state.
A redundancy circuit having a fuse set configured to produce a signal to repair a defective memory cell by using a laser beam radiating method, the fuse set, comprising:
- a fuse signal generating unit configured to receive an initializing signal and to generate a fuse power signal and a fuse signal;
- an address signal comparing unit configured to receive the initializing signal, the fuse power signal, the fuse signal, and an address signal, and to output a comparison signal;
- and
- a redundancy signal generating unit configured to receive an activated comparison signal and an activated fuse signal, and to output an activated redundancy signal.
A redundancy circuit having a fuse set producing a signal to repair a defective memory cell repair signal by using an electrical fusing method, the fuse set, comprising:
- a fuse signal generating unit configured to receive an initializing signal, a test mode signal, and a specific address signal, and to output a fuse signal;
- an address signal comparing unit configured to receive the initializing signal, the test mode signal, the specific address signal, and the address signal, and to output a comparison signal;
- and
- a redundancy signal generating unit configured to receive an activated comparison signal and an activated fuse signal, and to output an activated redundancy signal.
Dependencies are inferred from the claim text.