Multi-bit electromechanical memory devices and methods of manufacturing the same

A memory device comprising:

• a substrate;
• a bit line on the substrate extending in a first direction;
• a first word line structure on the bit line and spaced apart from, and insulated from, the bit line, the first word line structure extending in a second direction transverse to the first direction;
• an electrode coupled to the bit line extending over the first word line structure and spaced apart from the first word line structure by a first gap;
• and
• a second word line structure over the electrode and spaced apart from the electrode by a second gap, the second word line structure extending in the second direction,
• wherein one of the first word line structure and second word line structure comprises a charge trapping structure between a conductive layer of the one of the word line structures and the electrode, wherein the charge trapping structure is spaced apart from the electrode by a corresponding one of the respective first and second gaps;
• wherein the electrode is cantilevered between the first word line structure and the second word line structure such that the electrode deflects to be electrically coupled with a top portion of the first word line structure through the first gap in a first bent position and deflects to be electrically coupled with a bottom portion of the second word line structure through the second gap in a second bent position, and is isolated from the first word line structure and the second word line structure in a rest position.

A dual-bit memory device comprising:

• a substrate;
• a bit line on the substrate extending in a first direction;
• first and second lower word line structures on the bit line, the first and second lower word line structures being spaced apart from each other and spaced apart from, and insulated from, the bit line, each of the first and second lower word line structures extending in a second direction transverse to the first direction;
• first and second electrodes coupled to the bit line, the first electrode extending over the first lower word line structure and spaced apart from the first lower word line structure by a first lower gap;
• the second electrode extending over the second lower word line structure and spaced apart from the second lower word line structure by a second lower gap;
• and
• first and second upper word line structures over the respective first and second electrodes, the first and second upper word line structures being spaced apart from each other, the first upper word line structure being spaced apart from the first electrode by a first upper gap, the second upper word line structure being spaced apart from the second electrode by a second upper gap, each of the first and second upper word line structures extending in the second direction,
• wherein at least one pair of the first and second lower word line structures and the first and second upper word line structures comprises first and second charge trapping structures between first and second conductive layers of the respective first and second word line structures and the corresponding first and second electrodes, wherein the first and second charge trapping structures are spaced apart from the respective first and second electrodes by the respective first and second gaps,
• wherein the first electrode is cantilevered between the first lower word line structure and the first upper word line structure such that the first electrode deflects to be electrically coupled with a top portion of the first lower word line structure through the first lower gap in a first bent position and deflects to be electrically coupled with a bottom portion of the first upper word line structure through the first upper gap in a second bent position, and is isolated from the first lower word line structure and the first upper word line structure in a rest position, and
• wherein the second electrode is cantilevered between the second lower word line structure and the second upper word line structure such that the second electrode deflects to be electrically coupled with a top portion of the second lower word line structure through the second lower gap in a first bent position and deflects to be electrically coupled with a bottom portion of the second upper word line structure through the second upper gap in a second bent position, and is isolated from the second lower word line structure and the second upper word line structure in a rest position.

A dual-bit memory device comprising:

• a substrate;
• a bit line on the substrate extending in a first direction;
• first and second lower word lines on the bit line, the first and second lower word lines being spaced apart from each other and spaced apart from, and insulated from, the bit line, each of the first and second lower word lines extending in a second direction transverse to the first direction;
• first and second electrodes coupled to the bit line, the first electrode extending over the first lower word line and spaced apart from the first lower word line by a first lower gap;
• the second electrode extending over the second lower word line and spaced apart from the second lower word line by a second lower gap;
• and
• first and second upper word lines over the respective first and second electrodes, the first and second upper word lines being spaced apart from each other, the first upper word line being spaced apart from the first electrode by a first upper gap, the second upper word line being spaced apart from the second electrode by a second upper gap, each of the first and second upper word lines extending in the second direction,
• wherein the first electrode is cantilevered between the first lower word line and the first upper word line such that the first electrode deflects to be electrically coupled with a top portion of the first lower word line through the first lower gap in a first bent position and deflects to be electrically coupled with a bottom portion of the first upper word line through the first upper gap in a second bent position, and is isolated from the first lower word line and the first upper word line in a rest position, and
• wherein the second electrode is cantilevered between the second lower word line and the second upper word line such that the second electrode deflects to be electrically coupled with a top portion of the second lower word line through the second lower gap in a first bent position and deflects to be electrically coupled with a bottom portion of the second upper word line through the second upper gap in a second bent position, and is isolated from the second lower word line and the second upper word line in a rest position.