M-bit race delay adder and method of operation

A data processor comprising:

• an instruction execution pipeline comprising N processing stages, each of said N processing stages capable of performing one of a plurality of execution steps associated with a pending instruction being executed by said instruction execution pipeline, wherein at least one of said N processing stages comprises an M-bit adder capable of receiving a first M-bit argument, a second M-bit argument, and a carry-in (CI) bit, said M-bit adder comprising:
• M adder cells arranged in R rows, wherein a least significant adder cell in a first one of said rows of adder cells is operable to:
• receive a first data bit, AX, from said first M-bit argument and a first data bit, BX, from said second M-bit argument,
• generate both a first conditional carry-out bit, CX(1), and a second conditional carry-out bit, CX(0),
• provide the first and second conditional carry-out bits CX(1) and CX(0) to a second one of said adder cells, and
• wherein said CX(1) bit is calculated assuming a row carry-out bit from a second row of adder cells preceding said first row is a 1 and said CX(0) bit is calculated assuming said row carry-out bit from said second row is a 0;
• and
• wherein said second one of said adder cells in said first one of said rows is operable to:
• receive a first data bit, AX+1, from said first M-bit argument and a first data bit, BX+1, from said second M-bit argument,
• receive both said first conditional carry-out bit CX(1) and said second conditional carry-out bit CX(0);
• generate both a first conditional carry-out bit, CX+1(1), and a second conditional carry-out bit, CX+1(0), by propagating said first conditional carry-out bit CX(1) and said second conditional carry-out bit CX(0) through a first pass gate and a second pass gate, respectively, when said first data bit AX+1 and said second data bit BX+1 are not equal, and
• output said first and second conditional carry-out bits CX+1(1) and CX+1(0), and
• wherein said second adder cell further comprises:
• a first inverter operable for inverting said first conditional carry-out bit CX(1) transmitted through said first pass gate prior to outputting said first conditional carry-out bit CX(1);
• and
• a second inverter operable for inverting said second conditional carry-out bit CX(0) transmitted through said second pass gate prior to outputting said second conditional carry-out bit CX(0).

A method of adding a first M-bit argument and a second M-bit argument in an M-bit adder, the M-bit adder comprising M adder cells arranged in R rows, the method comprising:

• receiving a first data bit, AX, from the first M-bit argument and a first data bit, BX, from the second M-bit argument in a least significant adder cell in a first one of the rows of adder cells;
• calculating in the least significant adder cell a first conditional carry-out bit, CX(1), assuming a row carry-out bit from a second row of adder cells preceding the first row is a 1;
• calculating in the least significant adder cell a second conditional carry-out bit, CX(0), assuming the row carry-out bit from the second row is a 0;
• calculating in the least significant adder cell a first conditional sum bit, SX(1), assuming the row carry-out bit from the second row is a 1;
• calculating in the least significant adder cell a second conditional sum bit, SX(0), assuming the row carry-out bit from the second row is a 0;
• propagating the CX(1) bit and the CX(0) bit to a second adder cell in the first row of adder cells;
• selecting one of the SX(1) bit and the SX(0) bit to be output from the least significant adder cell according to a value of the row carry-out bit from the second row;
• and
• receiving a first data bit, AX+1, from the first M-bit argument and a first data bit, BX+1, from the second M-bit argument in the second adder cell in said first one of said rows of adder cells;
• generating in said second adder cell both a first conditional carry-out bit, CX+1(1), and a second conditional carry-out bit, CX+1(0), by propagating said first conditional carry-out bit CX(1) and said second conditional carry-out bit CX(0) through a first pass gate and a second pass gate, respectively, when said first data bit AX+1 and said second data bit BX+1 are not equal
• outputting said first and second conditional carry-out bits CX+1(1) and CX+1(0) to other circuitry;
• using a first inverter within said second adder cell, inverting said first conditional carry-out bit CX(1) transmitted through said first pass gate prior to outputting said first conditional carry-out bit CX(1);
• and
• using a second inverter within said second adder cell, inverting said second conditional carry-out bit CX(0) transmitted through said second pass gate prior to outputting said second conditional carry-out bit CX(0).

An M-bit adder capable of receiving a first M-bit argument, a second M-bit argument, and a carry-in (CI) bit comprising:

• M adder cells arranged in R rows, wherein a least significant adder cell in a first one of said rows of adder cells is operable to:
• receive a first data bit, AX, from said first M-bit argument and a first data bit, Bx from said second M-bit argument,
• generate both a first conditional carry-out bit, CX(1), and a second conditional carry-out bit, CX(0),
• provide the first and second conditional carry-out bits CX(1) and CX(0) to a second one of said adder cells, and
• wherein said CX(1) bit is calculated assuming a row carry-out bit from a second row of adder cells preceding said first row is a 1 and said CX(0) bit is calculated assuming said row carry-out bit from said second row is a 0;
• and
• wherein said second one of said adder cells within said first one of said rows is operable to:
• receive a first data bit, AX+1, from said first M-bit argument and a first data bit, BX+1, from said second M-bit argument,
• receive both said first conditional carry-out bit CX(1) and said second conditional carry-out bit CX(0),
• generate both a first conditional carry-out bit, CX+1(1), and a second conditional carry-out bit, CX+1(0) by propagating said first conditional carry-out bit CX(1) and said second conditional carry-out bit CX(0) through a first pass gate and a second pass gate, respectively, when said first data bit AX+1 and said second data bit BX+1 are not equal, and
• output said first and second conditional carry-out bits CX+1(1) and CX+1(0) to other circuitry,
• wherein said second adder cell further comprises:
• a first inverter operable for inverting said received conditional carry-out bit CX(1) prior to transmission through said first pass gate;
• and
• a second inverter operable for inverting said received second conditional carry-out bit CX(0) prior to transmission through said second pass gate.